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Joshi P.K.,RCOEM | Kapse A.,RCOEM
Proceedings of 2016 International Conference on Advanced Communication Control and Computing Technologies, ICACCCT 2016 | Year: 2016

Due to limited number of pins, built-in self-test (BIST) for embedded Random Access Memories (RAMs) usually exports the diagnostic data serially, which increases the overall diagnostic time. The proposed BIST reduce the diagnostic time by reducing number of bits required for exporting faulty address and fault syndrome. The fault address bits are reduced by exporting differential address and fault syndrome is compressed using march element based (MEB) compression. Simulation results show that the compression ratio is about 43.01% for a 4K∗ 16-bit memory. © 2016 IEEE.

Sahu C.,Malaviya National Institute of Technology, Jaipur | Agrawal N.,RCOEM
Proceedings - 2016 IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2016 | Year: 2016

In this paper, we have shown frequency response analysis of common-emitter (CE) amplifier using bipolar charge plasma transistor (BCPT) with a device-circuit approach of mixed-mode simulation. Furthermore, the passive elements are adjusted to obtain the proper operating point (Q-point) of the circuit. The mixed-mode simulation results exhibits that maximum gain of the BJT, symmetric BCPT and asymmetric BCPT are 7.3 dB, 13.5 dB, and 13.7 dB, respectively and unity gain frequency are 813 GHz, 116 GHz, and 132 GHz, respectively. The mixed-mode simulation frequency response is also validated using transfer function equation containing pole and zero through MATLAB. © 2016 IEEE.

Palekar S.,RCOEM | Narkhede N.,RCOEM
2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings | Year: 2016

With the advent of technology, digital signal processing applications are flourishing prominently in space, medical and many commercial related areas. RISC processor is the heart of many high speed applications of embedded and digital signal processing. Floating point representation has prevalent ascendancy over fixed point numbers as it endeavors dynamic range of values. Hence in this paper a high speed MIPS based 32 bit RISC processor with single precision floating point unit for DSP applications is proposed. The inclination of the entire design is towards improving the performance of floating point arithmetic unit so as the performance of the entire RISC processor is ameliorated. The proposed processor is proficient of executing arithmetic, logical, floating point, data transfer, memory, shifting and rotating instructions. The complex multiplication are frequently used in the DSP applications and thus a special instruction for complex multiplication is incorporated. The multiplication engross most of the time, power and area of any operation, on that account the multiplier are reduced in number from four to two as compared to conventional complex multiplication method. The design is coded in Verilog HDL, simulated on Xilinx ISE 13.1 and synthesized on Spartan 6. Results indicates that the proposed design is optimized in speed as well as in area. © 2016 IEEE.

Thote V.S.,RCOEM | Khetade V.E.,RCOEM
2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings | Year: 2016

The key player in the multi-clock domain system is the synchronizer. This synchronizer suffers from the effect of metastability and results in the failure of the circuit. Prevention of the synchronizer from the metastability is feasible. Metastable state occurs whenever there is a violation of setup and hold time i.e., uncontrolled and unpredictable change in data within setup and hold time window. In this paper, we proposed a new architecture of the synchronizer. It detects any transitions in data signal within metastability window. The closed loop gains of the cross-coupled inverter are controlled by the external signal. This signal will ensure the correct state of the synchronizer. The additional part of the latch comes into action when this ambiguity occurs. The correctness of the circuit functionality is verified using HSPICE and Tanner EDA at the 32nm technology. © 2016 IEEE.

Palekar S.,RCOEM | Narkhede N.,RCOEM
2016 IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, RTEICT 2016 - Proceedings | Year: 2016

Many fields of science, engineering, finance, mathematical optimization methods, Artificial Neural Networks, signal and image processing algorithms requires the operations and manipulations of real numbers. Floating-point operations are most extensively adopted approach for exploiting real numbers. The speed of Floating-point arithmetic unit is very crucial performance parameter which impinges the operation of the system. On that account a 32 bit floating point arithmetic unit is designed for different applications which insists for eminent speed. The intent of this design is to reduce the area and combinational path delay to enhance the speed of operation which is attained by parallelism in multiplier which is used for mantissa multiplication. For Floating-point multiplier Booth recoded multiplier is used where the number of partial product are reduced which in turns boost the speed of multiplication. The proposed module is implemented on Spartan 6 FPGA. Performance of the floating point arithmetic unit is compared with latest research papers regarding delay and it is ascertained that there is 59% of optimization in critical path delay of floating point multiplier and 50 % of optimization of floating point adder. The result illustrates that proposed arithmetic unit has a great impact on convalescent the speed and area of the design. © 2016 IEEE.

Tambe P.P.,RCOEM | Kulkarni M.S.,Indian Institute of Technology Delhi
Proceedings of the International Conference on Industrial Engineering and Operations Management | Year: 2016

Maintenance and quality control are the two important decisions in manufacturing industries whose effective planning can results in excellent performance of a production system. This paper presents a methodology for simultaneously optimizing the maintenance decision and control chart parameters for a multi-component system. The objective is to minimize the expected total cost of system operation of these two functions and identify the selective maintenance actions and control chart parameters, with availability, allowable maintenance time and average time to signal as constraints. The optimization of the proposed integrated model in this paper results into maintenance decision in terms of maintenance actions namely, repair, replace or do-nothing for the system components along with the values of parameters for sample size, a sampling interval and a coefficient of control limits. A numerical example is presented to demonstrate the approach. © IEOM Society International. © IEOM Society International.

Joshi P.,RCOEM | Sahu I.,RCOEM
IEEE International Conference on Innovative Mechanisms for Industry Applications, ICIMIA 2017 - Proceedings | Year: 2017

In today's world power dissipation is one of the major concern as the complexity of the chip is increasing and more devices are being integrated on a single chip. Thus this high density of chip and increased power dissipation demands for better power optimization methods. Reversible logic is one of the method to reduce power dissipation. Reversible computing has a wide number of applications in areas of advance computing such as low power CMOS VLSI design, nanotechnology, cryptography, optical computing, DNA computing and quantum computing. This paper presents reversible T-flip flop using 'SGG' gate and Feynman gate and then a novel design of asynchronous reversible counter is also proposed. © 2017 IEEE.

Hardas B.M.,RCOEM
Proceedings of the 2016 IEEE International Conference on Wireless Communications, Signal Processing and Networking, WiSPNET 2016 | Year: 2016

This paper investigates a novel technique called as pilot assisted techniques for PAPR reduction in orthogonal frequency division multiplexing (OFDM). A pilot assisted technique has been implemented in MATLAB for AWGN and Rayleigh channel. PAPR has been found out for AWGN and Rayleigh channel. Also the Bit error rate (BER) vs frame for each channel has been evaluated. © 2016 IEEE.

Agrawal P.,RCOEM
2014 International Conference on Signal Processing and Integrated Networks, SPIN 2014 | Year: 2014

Vehicular Ad hoc Network (VANET) is the network of vehicles and road side units. The effective routing protocol is needed to route the data from source node to destination node in VANET. In available protocols, Directed Route Node Selection (DRNS) cannot detect the nodes movement in multiple directions for routing and in Ad hoc On-Demand Multipath Distance Vector (AOMDV) the route are not much stable. But DRNS is unable to detect nodes movement in other directions and specifically suited for the highway scenarios. A novel protocol, Acute direction Route Node Selection Multipath (ADRNSM) routing is proposed which is multipath protocol and adapt to 16 different directions of movement. This protocol is basically introduced to be aware of movement direction and engage nodes moving only in specific direction for routing to destination node. This protocol finds multiple paths to destination node and avoids engaging the nodes moving in other directions to increase the performance in urban scenario unlike DRNS protocol. © 2014 IEEE.

Hemnani M.,RCOEM
2016 IEEE Students' Conference on Electrical, Electronics and Computer Science, SCEECS 2016 | Year: 2016

The complexity of many image processing applications and their stringent performance requirements have come to a point where they can no longer meet the real time deadlines, if implemented on conventional architectures based on a single general-purpose processor. Acceleration of these algorithms can be done by parallel computing. Parallelism can be accomplished both at hardware and software levels by various tools and methodologies. The various methods hence discussed prove to be helpful and thus a combination of both the custom hardware and software tool helps in speeding up the image processing algorithm. Different methodologies that can be used for parallel computation are discussed. © 2016 IEEE.

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