Agency: European Commission | Branch: FP7 | Program: JTI-CP-ARTEMIS | Phase: SP1-JTI-ARTEMIS-2010-4;SP1-JTI-ARTEMIS-2010-1 | Award Amount: 7.76M | Year: 2011
The PRESTO project aims at improving test-based embedded systems development and validation, while considering the constraints of industrial development processes. This project is based on the integration of (a) test traces exploitation (generated by test execution in the software integration phase induced by the industrial development process, to validate the requirements of the system) along with (b) platform models and (c) design space exploration techniques. The expected result of the project is to enable functional and performance analysis and platform optimisation at early stage of the design development. The approach of PRESTO is to model the software/hardware allocation, by the use of a modelling framework based on the UML profile for model-driven development of Real Time and Embedded Systems (MARTE). The analysis tools, among them timing analysis including Worst Case Execution Time (WCET) analysis, scheduling analysis and possibly more abstract system-level timing analysis techniques will receive as inputs on the one hand information from the MARTE performance modelling of the HW/SW-platform, and on the other hand behavioural information of the software design from tests results of the integration test execution. Of particular novelty in PRESTO is the exploitation of traces for the exclusion of over-pessimistic assumptions during timing analysis: instead of taking all possible inputs and states into account for a worst-case analysis, a set of relevant traces is analyzed separately to reduce the set of possible inputs and states for each trace. A particular attention will be given to industrial development constraints, which means 1) as little cost as possible in term of extra specification time and need of expertise, 2) a simple use of the tools, 3) a smooth integration in the current design process, 4) a tool framework flexible enough to be adapted to different process methodologies, design languages and integration test frameworks, 5) analysis results DoW (TA) Approved by the ARTEMIS JU on 26/05/2014
Agency: European Commission | Branch: FP7 | Program: JTI-CP-ARTEMIS | Phase: SP1-JTI-ARTEMIS-2011-1 | Award Amount: 18.93M | Year: 2012
New safety standards, such as ISO 26262, present a challenge for companies producing safety-relevant embedded systems. Safety verification today is often ad-hoc and manual; it is done differently for digital and analogue, hardware and software. The VeTeSS project will develop standardized tools and methods for verification of the robustness of safety-relevant systems, particularly against transient common-cause faults. Bringing together partners from every part of the supply chain, VeTeSS will develop automated, quantitative processes usable at all stages of development. These will provide standardized data from verification for safety standards qualification. Development costs and time to market will be reduced, even with the increasing complexity of embedded systems and software. European industry will benefit from vendors being able to supply standard components for multiple applications, rather than products designed to a specific customers requirements. To test these as safety elements out of context, assumptions must be made about the environment in which they will be used. A standardized, evidence-based verification process will enable this reuse of components in different applications. The focus of VeTeSS is the strategically important automotive market. There are other industries with similar requirements and we will actively engage with those to share knowledge and disseminate results. The proposed developments are relevant to conventional vehicles as well as to new electric/hybrid vehicles. The safety of the latter needs to be proven to allow wider adoption, which will in turn be an important contribution to carbon emissions reduction. The results of the project will improve the competitiveness of the European embedded hardware and software industry. It will improve the safety, quality and reliability of products and enabling innovative technologies to increase road user safety. It will also benefit society by reducing accidents and related costs. 1. Approved by ARTEMIS-JU on 22/02/2012. 2. Updates approved for JUGA amendment No.1 by ARTEMIS-JU on 29/04/2013 3. Updates approved for JUGA amendment No.2 by ARTEMIS-JU on 8 May 2014, finally approved by ECSEL-JU on 21/11/2014
Agency: European Commission | Branch: H2020 | Program: ECSEL-RIA | Phase: ECSEL-07-2015 | Award Amount: 20.53M | Year: 2016
Embedded systems have significantly increased in technical complexity towards open, interconnected systems. This has exacerbated the problem of ensuring dependability in the presence of human, environmental and technological risks. The rise of complex Cyber-Physical Systems (CPS) has led to many initiatives to promote reuse and automation of labor-intensive activities. Two large-scale projects are OPENCOSS and SafeCer, which dealt with assurance and certification of software-intensive critical systems using incremental and model-based approaches. OPENCOSS defined a Common Certification Language (CCL), unifying concepts from different industries to build a harmonized approach to reduce time and cost overheads, via facilitating the reuse of certification assets. SafeCer developed safety-oriented process lines, a component model, contract-based verification techniques, and process/product-based model-driven safety certification for compositional development and certification of CPSs. AMASS will create and consolidate a de-facto European-wide assurance and certification open tool platform, ecosystem and self-sustainable community spanning the largest CPS vertical markets. We will start by combining and evolving the OPENCOSS and SafeCer technological solutions towards end-user validated tools, and will enhance and perform further research into new areas not covered by those projects. The ultimate aim is to lower certification costs in face of rapidly changing product features and market needs. This will be achieved by establishing a novel holistic and reuse-oriented approach for architecture-driven assurance (fully compatible with standards e.g. AUTOSAR and IMA), multi-concern assurance (compliance demonstration, impact analyses, and compositional assurance of security and safety aspects), and for seamless interoperability between assurance/certification and engineering activities along with third-party activities (external assessments, supplier assurance).
Agency: European Commission | Branch: FP7 | Program: JTI-CP-ARTEMIS | Phase: SP1-JTI-ARTEMIS-2011-5 | Award Amount: 16.56M | Year: 2012
ICT-based service and product innovation is curtailed by the growing vertical chain of dependence on poorly interoperable proprietary technologies in Europe. This issue was identified to have high impact on European innovation productivity by the Report of the Independent Expert Group on R&D and Innovation, commonly known as the Aho-report. The report demanded incentives for the convergence of shared technologies and markets as a remedy. Actions creating standardized, commercially exploitable yet widely accessible ecosystems in European priority areas should be publicly supported. Real-time applications for heterogeneous, networked, embedded many-core systems suffer from the lack of trusted pathways to system realization and application deployment. Service and product development efforts are high with many uncertainties discouraging such ventures. This project brings to bear a holistically designed ecosystem from application to silicon. The ecosystem is realized as a tightly integrated multi-vendor solution and tool chain complementing existing standards. Feature-limited releases of reference tools and platforms are made available under favourable licensing conditions to support the evaluation and adoption of the results. Full-fledged versions are retained for commercial exploitation and standardization of the overall ecosystem is pursued. As direct effects of the project results 30% reduction of the total cost of ownership, 50% shorter time-to-market, and 30% decrease of the number of development assets are expected. Marketable lead applications driving ecosystem development and benchmarking on the fields of industrial & intelligent transport systems, video & image processing, and wireless communications are produced. Key challenges include guaranteeing secure, reliable, and timely operation, back-annotation based forward system governance, Tool-tool, tool-middleware, and middleware-hardware exchange interfaces, and energy management with minimal run-time overhead. Approved by ECSEL-JU on 03/02/2015
Agency: European Commission | Branch: FP7 | Program: CP | Phase: ICT-2011.3.4 | Award Amount: 4.58M | Year: 2011
Engineers who design hard real-time embedded systems express a need for several times the performance available today while keeping safety as major criterion. A breakthrough in performance is expected by parallelising hard real-time applications. parMERASA targets a timing analysable system of parallel hard real-time applications running on a scalable multi-core processor. Several new scientific and technical challenges will be tackled in the light of timing analysability: parallelisation techniques for industrial applications, operating system virtualisation and efficient synchronisation mechanisms, guarantee of worst-case execution times (WCET) of parallelised applications, verification and profiling tools, and scalable memory hierarchies together with I/O systems for multi-core processors.\nThe output of parMERASA will be at least an eightfold performance improvement of the WCET for parallelised legacy applications in avionics, automotive, and construction machinery domains in comparison to the original sequential versions. The execution platform, i.e. the parMERASA multi-core processor and system software, will provide temporal and spatial isolation between tasks and scale up to 64 cores. A software engineering approach will be taken targeting at least four parallel execution patterns that are analysable. Verification and profiling tools will be developed, and we aim to provide at least four recommendations to enhance both automotive and avionic standards.\nparMERASA will impact new products for transportation systems and industrial applications. It will impact standards by introducing parallel execution and time predictability as key features. This will contribute to reinforce the EC position in the field of critical computing systems and yield an advantage for European industry in the highly competitive avionics, automotive, and construction machinery markets.
Agency: European Commission | Branch: FP7 | Program: CP | Phase: ICT-2009.3.4 | Award Amount: 2.60M | Year: 2010
There is an ever-increasing demand both for new functionality and for reduced development and production costs for all kinds of Critical Real-Time Embedded (CRTE) systems (safety, mission or business critical). Moreover, new functionality demands can only be delivered by more complex software and aggressive hardware acceleration features like memory hierarchies and multicore processors. However, these greatly increase system complexity, making it much more difficult to analyse applications for their temporal behaviour. Another key problem of CRTE systems is the need to prove that they operate correctly, satisfying all temporal constraints. The current generation of platforms, despite being based on comparatively simple and old processor technologies, are already extremely difficult to analyse for their temporal behaviour, and resulting errors in operation, cost EU industries billions of Euros annually in warranty and post-production costs.\n\nThe PROARTIS thesis is that the timing behaviour of systems that use advanced hardware features like multicore CPUs and complex memory hierarchies can be analysed effectively by probabilistic timing analysis techniques that reduce the risk of temporal pathological cases to quantifiably negligible levels. Preliminary research results in cache replacement policies by members of the PROARTIS consortium strongly support this claim. PROARTIS defines new hardware and software architecture paradigms based on the concept of randomisation that, with minimal changes to current processes and methods, guarantee timing behaviours that can be analysed with probabilistic techniques. PROARTIS uses a holistic approach in which probabilistic analysis extends from hardware design, compiler and real time operating system to applications. On top of this platform, we will build probabilistic timing analysis methods based on current commercial tools. We will validate our approach via an industrial case study.
Agency: European Commission | Branch: FP7 | Program: CP | Phase: ICT-2013.3.4 | Award Amount: 6.79M | Year: 2013
In the next decade, EU industries developing Critical Real-Time Embedded Systems (CRTES) (safety, mission or business critical) will face a once-in-a-life-time disruptive challenge caused by the transition to multicore processors and the advent of manycores, tantamount to complex networked systems. This challenge brings the opportunity to integrate multiple applications onto the same hardware platform bringing significant advantages in performance, production costs, and reliability. It also brings a severe threat relating to a key problem of CRTES; the need to prove that all temporal constraints will be satisfied during operation. Current CRTES, based on relatively simple singlecore processors, are already extremely difficult to analyse for temporal behaviour, resulting in errors in operation costing EU industry billions each year. The advent of multicore and manycore platforms exacerbates this problem, rendering traditional temporal analysis techniques ineffectual. A new approach is needed.\nThe PROXIMA thesis is that the temporal behaviour of mixed-criticality CRTES executing on multicore and manycore platforms can be analysed effectively via innovative probabilistic techniques. PROXIMA defines new hardware and software architectural paradigms based on the concept of randomisation. It extends this approach across the hardware and software stack ensuring that the risks of temporal pathological cases are reduced to quantifiably small levels. On top of this, PROXIMA builds a comprehensive suite of probabilistic analysis methods integrated into commercial design, development, and verification tools, complemented by appropriate arguments for certification. PROXIMA provides a complete infrastructure; harnessing the full potential of new processor resources, demonstrating and supporting effective temporal analysis, bringing the probabilistic approach to a state of technological readiness, and priming multiple EU industry sectors in its use via a number of case studies.
Agency: GTR | Branch: Innovate UK | Program: | Phase: European | Award Amount: 220.92K | Year: 2012
Agency: GTR | Branch: Innovate UK | Program: | Phase: Smart - Development of Prototype | Award Amount: 236.45K | Year: 2014
This project addresses the opportunity to develop a new verification tool for the Safety Critical Systems (SCS) market. We will develop a prototype tool RapiMV, the Rapita Model Verifier, to become a new component in our existing Rapita Verification Suite (RVS). RapiMV fills a void in the market in two key safety critical markets: Aerospace and Automotive. It introduces model checking tools for more automation, and a new approach to gathering data to reduce costs and widen tool applicability.
Agency: GTR | Branch: Innovate UK | Program: | Phase: European | Award Amount: 207.35K | Year: 2012
Awaiting Public Project Summary