Los Altos, CA, United States
Los Altos, CA, United States

Rambus Incorporated, founded in 1990, is an American technology licensing company known for developing RDRAM. The company is also well known for its intellectual property-based litigation following the introduction of DDR-SDRAM memory, leading some to label the company as a patent troll. Wikipedia.


Time filter

Source Type

An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuits jitter tolerance.


A light guide includes opposed major surfaces, a light input edge extending therebetween, and light extracting elements at at least one of the major surfaces. At least a portion of the light extracting elements includes: a longitudinal axis extending between a first end and a second end of the light extracting element; a first side surface and a second side surface each extending from the major surface; and a ridge or end surface connecting the first side surface and the second side surface, the ridge or end surface extending along the longitudinal axis in a non-linear, winding path as viewed from a direction orthogonal to the major surface. In some embodiments, a cover element includes light redirecting elements having a ridge or end surface extending along a longitudinal axis of the element in a non-linear, winding path as viewed from a direction orthogonal to the major surface.


Patent
Rambus | Date: 2016-08-31

A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.


Patent
Rambus | Date: 2016-08-26

Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.


A memory is disclosed comprising a first memory portion, a second memory portion, and an interface, wherein the memory portions are electrically isolated from each other and the interface is capable of receiving a row command and a column command in the time it takes to cycle the memory once. By interleaving access requests (comprising row commands and column commands) to the different portions of the memory, and by properly timing these access requests, it is possible to achieve full data bus utilization in the memory without increasing data granularity.


A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.


A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around defective data connections to maintain full capacity and continue to support memory transactions.


Patent
Rambus | Date: 2016-08-22

The embodiments herein describe technologies of cryogenic digital systems with a power supply located in an ambient temperature domain and logic located in a cryogenic temperature domain. A pair of conductors is operable to carry current with a voltage difference between the power supply and the logic. The pair of conductors includes a first portion thermally coupled to a temperature-regulated or temperature-controlled intermediate temperature domain. The intermediate temperature domain is less than the ambient temperature domain and greater than the cryogenic temperature domain.


A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the invention, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations.


Patent
Rambus | Date: 2017-02-15

A sensing device projects near-field spatial modulations onto a closely spaced photodetector array. Due to physical properties of the grating, the point-spread response distributes spatial modulations over a relatively large area on the array. The spatial modulations are captured by the array, and photographs and other image information can be extracted from the resultant data. An image-change detector incorporating such a sensing device uses very little power because only a small number of active pixels are required to cover a visual field.

Loading Rambus collaborators
Loading Rambus collaborators