Munich, Germany
Munich, Germany

Qimonda AG was a memory company split out of Infineon Technologies on 1 May 2006, to form at the time the second largest DRAM company worldwide, according to the industry research firm Gartner Dataquest. It is now a patent licensing firm. Headquartered in Munich, Germany, Qimonda was a 300 mm manufacturer, and was one of the top suppliers of DRAM products for the PC and server markets. Infineon still controls a 77.5% stake, which it has written down . Infineon was on record as having the aim of divesting itself of this stake, with the purpose of becoming a minority stakeholder in 2009. The company has issued 42 million ADR shares, each ADR share representing one ordinary share in Qimonda.At its height in 2007, Qimonda employed approximately 13,500 personnel worldwide, from whom 1,800 were employed in R&D with access to four 300 mm manufacturing sites and operating six major R&D facilities, and included a chip packaging complex in Vila do Conde, Portugal, and its lead R&D center in Dresden, Germany, in total covering three continents. During this time, and on into September 2008, the price of DRAM continued to decline due to market oversupply, resulting in significant corporate financial losses throughout 2008. Wikipedia.

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Patent
Qimonda AG | Date: 2013-07-12

A memory system having a plurality of memory cells for storing payload data and redundancy data. The memory system having a read-out circuit configured to read-out a status of the plurality of memory cells, the read-out status having payload data, redundancy data and associated reliability information. Moreover, the memory system has a data processor configured to derive the payload data from the read-out status using the reliability information.


Patent
Qimonda AG | Date: 2012-04-10

An embodiment of a circuit comprises an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a command/address interface coupled to an input of the output buffer, a memory core coupled to the input of the output buffer, and a controller circuit configured to cause data stored within the output buffer to be output to the data interface, further configured to cause data stored within the memory core to be output to the input of the output buffer, so that the data is stored within the output buffer, and further configured to cause provision of data received at the command/address interface to the input of the output buffer, so that the data is stored within the output buffer.


Patent
Qimonda AG | Date: 2011-03-17

An integrated device is disclosed. In one embodiment, the integrated device includes a carrier substrate with a through hole and a contact sleeve. A circuit chip is provided with a contact pad above the carrier substrate. A conductive material electrically connects the contact pad to the contact sleeve.


Patent
Qimonda AG | Date: 2014-07-09

A circuit module has a module board (300) and a plurality of circuit chips (302) that are arranged on the module board. A module main bus (308) having a plurality of lines of the circuit module branches into a plurality of sub-buses (310) having a plurality of lines. Each of the sub-buses is connected to one of the circuit chips. Each circuit chip comprises an indication signal generating unit (314) for providing an indication signal (346) based on a combination of the signals received on the plurality of lines of the sub-bus connected to the respective circuit chip, and an indication signal output (350) for outputting the indication signal.


Patent
Qimonda AG | Date: 2012-01-30

One embodiment relates to an integrated circuit that includes a memory array of pillars arranged in rows and columns. The pillars are separated from one another by row trenches and column trenches. The column trenches include a pair of parallel column trenches. A first trench of the pair includes two parallel bit lines coupled to pillars adjacent to the first trench. A second trench of the pair is free of bit lines. Other methods, devices, and systems are also disclosed.


Patent
Qimonda AG | Date: 2011-01-26

A method of manufacturing a memory cell includes: forming a first electrode, depositing a first insulator material over the first electrode, forming a via in the first insulator material, depositing a resistivity changing material in the via without completely filling the via, and forming a second electrode contacting the resistivity changing material.


A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module.


An integrated circuit includes a first electrode, a second, a first resistivity changing material contacting the first electrode at a first interface, and a second resistivity changing material contacting the second electrode at a second interface. A direct communication path between the first interface and the second interface is greater than the lateral distance.


Patent
Qimonda AG | Date: 2013-06-25

A semiconductor memory chip including error correction circuitry configured to receive data words from an external device, each data word comprising a binary number of data bits, and configured to error encode each data word to form a corresponding coded word comprising a non-binary number of data bits including the data bits of the data word and a plurality of error correction code bits. At least one memory cell array is configured to receive and store the coded word and partitioned based on the non-binary number of bits of the coded word so as to have a non-binary number of wordlines and provide the memory chip with an aspect ratio other than a 2:1 aspect ratio.


Patent
Ibm, Qimonda AG and Macronix International Co. | Date: 2013-11-07

An integrated circuit includes a substrate including isolation regions, a first conductive line formed in the substrate between isolation regions, and a vertical diode formed in the substrate. The integrated circuit includes a contact coupled to the vertical diode and a memory element coupled to the contact. The first conductive line provides a portion of the vertical diode.

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