Qimonda AG was a memory company split out of Infineon Technologies on 1 May 2006, to form at the time the second largest DRAM company worldwide, according to the industry research firm Gartner Dataquest. It is now a patent licensing firm. Headquartered in Munich, Germany, Qimonda was a 300 mm manufacturer, and was one of the top suppliers of DRAM products for the PC and server markets. Infineon still controls a 77.5% stake, which it has written down . Infineon was on record as having the aim of divesting itself of this stake, with the purpose of becoming a minority stakeholder in 2009. The company has issued 42 million ADR shares, each ADR share representing one ordinary share in Qimonda.At its height in 2007, Qimonda employed approximately 13,500 personnel worldwide, from whom 1,800 were employed in R&D with access to four 300 mm manufacturing sites and operating six major R&D facilities, and included a chip packaging complex in Vila do Conde, Portugal, and its lead R&D center in Dresden, Germany, in total covering three continents. During this time, and on into September 2008, the price of DRAM continued to decline due to market oversupply, resulting in significant corporate financial losses throughout 2008. Wikipedia.
Qimonda AG and United Test And Assembly Center Ltd. | Date: 2011-10-20
A method of mounting a semiconductor die on a substrate with a solder mask on a first surface includes placing a die on the solder mask, and mounting the die to the substrate by applying pressure and heat. The applied pressure ranges from a bond force of approximately 5 to 10 Kg, the heat has a temperature range from approximately 150 to 200 C. and the pressure is applied for a range of approximately 1 to 10 seconds.
Qimonda AG | Date: 2010-11-04
Integrated circuit and programmable delay. One embodiment provides an integrated circuit including a programmable delay element having a plurality of single delay cells. The delay cells include a first input and a second input and a first output. The delay cells are arranged to form a chain such that the first output of a preceding delay cell is coupled to the second input of a successive delay cell. The first inputs of any delay cells are configured to receive an input signal to be delayed. The delay cells out of the plurality of delay cells is configured to constitute a starting point of a signal path including any of the delay cells arranged downstream of the starting point. The first output of the last delay cell in the chain forms an output of the programmable delay element.
Qimonda AG | Date: 2012-01-30
One embodiment relates to an integrated circuit that includes a memory array of pillars arranged in rows and columns. The pillars are separated from one another by row trenches and column trenches. The column trenches include a pair of parallel column trenches. A first trench of the pair includes two parallel bit lines coupled to pillars adjacent to the first trench. A second trench of the pair is free of bit lines. Other methods, devices, and systems are also disclosed.
Qimonda AG | Date: 2013-06-25
A semiconductor memory chip including error correction circuitry configured to receive data words from an external device, each data word comprising a binary number of data bits, and configured to error encode each data word to form a corresponding coded word comprising a non-binary number of data bits including the data bits of the data word and a plurality of error correction code bits. At least one memory cell array is configured to receive and store the coded word and partitioned based on the non-binary number of bits of the coded word so as to have a non-binary number of wordlines and provide the memory chip with an aspect ratio other than a 2:1 aspect ratio.
Qimonda AG | Date: 2012-04-10
An embodiment of a circuit comprises an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a command/address interface coupled to an input of the output buffer, a memory core coupled to the input of the output buffer, and a controller circuit configured to cause data stored within the output buffer to be output to the data interface, further configured to cause data stored within the memory core to be output to the input of the output buffer, so that the data is stored within the output buffer, and further configured to cause provision of data received at the command/address interface to the input of the output buffer, so that the data is stored within the output buffer.