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Atlanta, GA, United States

Spicer R.,Qcept Technologies
Solid State Technology

Wafer cleaning and surface preparation are the most repeated steps in the fab, up to 100 times per wafer, which means there are many opportunities for a sub-optimal cleaning process to cause catastrophic yield loss. The goal of wafer cleaning is to clean the wafer aggressively enough to remove unwanted material without damaging the underlying structures or substrate. Wafer cleaning can potentially damage these films or change their dielectric constant, either of which impacts device performance. In addition, the transition from polysilicon to metal gates at the 22nm node creates new wafer cleaning challenges. The industry has introduced physical methods, such as single-wafer (spray) cleans and acoustic (megasonic) vibration, to increase the physical action on the wafer surface, allowing less aggressive chemistries to be used. Source

Qcept Technologies | Date: 2014-09-26

Electronic instruments, namely, computer hardware, software and calibration devices sold as a unit for use in the rapid surface electric and topographic metrology inspection and calibration of semiconductor and wafer process examination and for quality control.

Qcept Technologies | Date: 2006-07-25

Electronic inspection apparatus consisting of and containing related computer processing and software components that are packaged together as a single functional apparatus unit for inspection, quality control and assurance, namely, rapid chemical metrology inspection, for material surface examination and processing.

Park J.,Samsung | Cho S.,Qcept Technologies | Hawthorne J.,Qcept Technologies
IEEE Transactions on Semiconductor Manufacturing

In this paper we discuss the detection, investigation and remediation of a silicon pitting defect in gate oxide patterning processes. The pitting defect is detected by optical inspection after an oxide wet etch operation. The cause of the physical defect is discovered as the result of Non-Visual Defect (NVD) inspection at process steps prior to the wet etch. A particular type of NVD, electric charge on a photoresist film, is detected at a process step immediately prior to the wet etch. A positive charge exceeding a specific level is highly correlated with the pitting defect, which only occurred on silicon that is doped to create an excess of free holes (p-type silicon). The manufacturing process is modified to reduce the level of process-induced charge, which also reduces the occurrence of pitting defects. A similar pitting defect is subsequently detected on a second manufacturing line at a different technology node. In this case, our investigation reveals that high negative charge on photoresist resulted in pitting only on silicon that is doped to create an excess of electrons (n-type silicon). Finite element modeling is used to identify a possible explanation for the charge-induced pitting defect. © 1988-2012 IEEE. Source

Park J.,Samsung | Cho S.,Qcept Technologies | Hawthorne J.,Qcept Technologies
Solid State Technology

The detection and investigation of a silicon pitting defect was investigated using standard optical inspection after an oxide wet etch operation. A wafer with a thermal oxide film was coated with photoresist. The resist was then patterned using lithography. This created openings in the photoresist where the oxide film will be removed by the wet etch process. An optical inspection is performed after lithography and prior to the etch operation. A wet etch of the oxide film was then performed in a low ammonium fluoride liquid (LAL), after which the photoresist was removed and the wafer cleaned. Finally, an optical After Clean Inspection (ACT) of the etched wafer was performed. The pitting defect was detected at ACT on 100% of the production wafers, and the defect maps showed strong correlation to end of line yield. The success in reducing pitting defects by reducing surface charge provides strong evidence that charge on the photoresist prior to oxide etch was a direct cause of the pitting. Source

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