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Austin, TX, United States

Agency: National Aeronautics and Space Administration | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 125.00K | Year: 2014

Integrated circuits in NASA spacecraft and Robotic Exploration Technologies that enable exploration of the solar system planets, moons and small bodies must operate over large temperature extremes and mitigate radiation effects that can result in upset or destruction of devices. Development of a reliable, high-performance nonvolatile memory (NVM) is critical to successful NASA explorations and development of robotic exploration technologies designed to operate in the extreme temperature, pressure and radiation environments of planetary and lunar surfaces. PrivaTran has previously demonstrated an electronically-programmable resistor as a NVM element. Initial static data retention testing has shown tolerance to several radiation types and high thermal stress, thereby demonstrating the potential for use in radiation-hardened circuits for extreme environments. Device materials and fabrication processes are compatible with high-temperature semiconductor manufacturing platforms utilizing wide-bandgap semiconductor materials. The PrivaTran NVM device uses standard materials as the active switching medium and device electrodes can be formed either in the substrate material or within the interconnect layers of the integrated circuit (IC). As a result, NVM arrays can be integrated with wide-band-gap semiconductor materials in a three-dimensional (3D) architecture, resulting in a high-density memory with superior NVM performance and significant savings in size, weight, power and cost.

Privatran | Date: 2013-03-11

A device with programmable resistance comprising memristive material between conductive electrodes on a substrate or in a film stack on a substrate is provided. During fabrication of a memristive device, a memristive layer may be hydrated after deposition of the memristive layer. The hydration of the memristive layer may be performed utilizing thermal annealing in a reducing ambient, implant or plasma treatment in a reducing ambient, or a deionized water rinse. Additionally, plasma-assisted etching of an electrode may be performed with hydration or in place of hydration to electroform devices in a batch, in situ process. The memristive device may be electroformed at low voltage and passivated to allow for device operation in air. Further, the memristive device is suitable for high throughput manufacturing.

Agency: National Aeronautics and Space Administration | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 99.99K | Year: 2011

Integrated circuits in NASA spacecraft and vehicle electronics must operate over large temperature extremes and mitigate radiation effects that can result in upset and/or destruction of devices. PrivaTran has previously demonstrated a two-terminal, electronically-programmable resistor as a nonvolatile memory (NVM) element with performance metrics exceeding those of competing technologies, and herein proposes this device as a radiation hardened NVM array formed within the metal interconnect layers of the integrated circuit and fully integrated in a 3D architecture, resulting in significant savings in weight, power and reliability.

Agency: NSF | Branch: Standard Grant | Program: | Phase: | Award Amount: 468.97K | Year: 2011

This Small Business Innovation Research (SBIR) Phase II project will further develop a two-terminal, electronically-programmable, nonvolatile memory array using materials commonly found in integrated circuit (IC) manufacturing. Each element is smaller than a single transistor and is formed using standard IC layers. This results in a three-dimensional (3D) integrated memory (3DIM) architecture achieved using a single substrate without need to assemble multiple die or wafers together with advanced bonding techniques. The ON/OFF conductance ratio and switching speed of these devices exceed the performance of competing technologies. Current flows through nanometer-sized regions of the device, and, as a result, the memory elements will scale to smaller dimensions without reducing the current through the device, thereby resulting in a dense memory array architecture with improved signal-to-noise ratio for each subsequent IC technology. The proposed overall program will include integrating a passivation layer, connecting each element with an isolation diode, optimizing device architecture to minimize footprint, and implementing 3DIM control and drive interface electronics. The program proposed herein addresses the topic by providing material innovations for improved performance in electronics where nano-scale semiconducting filaments are fabricated within a dielectric material for commercial data storage applications.

The broader impact/commercial potential of this project are in the areas of microelectronics chip manufacturing for wireless, mobile internet and other portable devices using nonvolatile memory. Memristive device arrays impact numerous commercial markets including flash and embedded memory, and offer orders of magnitude more density as compared to conventional memory. By implementing massively dense 3D memory array architecture on a single substrate, there is no need to fabricate multiple substrates and bond them together, thereby simplifying the fabrication process, reducing manufacturing cost and increasing yield. In addition to portable devices, the proposed device may find applications in space-based earth sciences and astronomy since it is tolerant to x-ray and heavy ion radiation. Some recent approaches to achieve 3D memory on a single substrate have not been successful due to problems with external fields causing bit errors and low signal-to-noise ratio, or because device operation is based on thermal, ionic transport, or phase-change mechanisms that are inherently slow. The proposed memory elements are controlled using electrical signals rather than thermal or chemical energy, making them highly efficient and faster than competing technologies. Memory arrays will be fabricated in a commercial foundry and scaled to smaller dimensions throughout the Phase II project.

Privatran and Rice University | Date: 2011-09-08

Various embodiments of the present invention pertain to memresistor cells that comprise: (1) a substrate; (2) an electrical switch associated with the substrate; (3) an insulating layer; and (3) a resistive memory material. The resistive memory material is selected from the group consisting of SiO

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