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Patent
Privatran and Rice University | Date: 2011-09-08

Various embodiments of the present invention pertain to memresistor cells that comprise: (1) a substrate; (2) an electrical switch associated with the substrate; (3) an insulating layer; and (3) a resistive memory material. The resistive memory material is selected from the group consisting of SiO_(x), SiO_(x)H, SiO_(x)N_(y), SiO_(x)N_(y)H, SiO_(x)Cz, SiO_(x)C_(z)H, and combinations thereof, wherein each of x, y and z are equal or greater than 1 or equal or less than 2. Additional embodiments of the present invention pertain to memresistor arrays that comprise: (1) a plurality of bit lines; (2) a plurality of word lines orthogonal to the bit lines; and (3) a plurality of said memresistor cells positioned between the word lines and the bit lines. Further embodiments of the present invention provide methods of making said memresistor cells and arrays.


Patent
Privatran | Date: 2013-03-11

A device with programmable resistance comprising memristive material between conductive electrodes on a substrate or in a film stack on a substrate is provided. During fabrication of a memristive device, a memristive layer may be hydrated after deposition of the memristive layer. The hydration of the memristive layer may be performed utilizing thermal annealing in a reducing ambient, implant or plasma treatment in a reducing ambient, or a deionized water rinse. Additionally, plasma-assisted etching of an electrode may be performed with hydration or in place of hydration to electroform devices in a batch, in situ process. The memristive device may be electroformed at low voltage and passivated to allow for device operation in air. Further, the memristive device is suitable for high throughput manufacturing.


Grant
Agency: National Aeronautics and Space Administration | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 99.99K | Year: 2011

Integrated circuits in NASA spacecraft and vehicle electronics must operate over large temperature extremes and mitigate radiation effects that can result in upset and/or destruction of devices. PrivaTran has previously demonstrated a two-terminal, electronically-programmable resistor as a nonvolatile memory (NVM) element with performance metrics exceeding those of competing technologies, and herein proposes this device as a radiation hardened NVM array formed within the metal interconnect layers of the integrated circuit and fully integrated in a 3D architecture, resulting in significant savings in weight, power and reliability.


Grant
Agency: Department of Defense | Branch: Navy | Program: SBIR | Phase: Phase II | Award Amount: 749.96K | Year: 2011

PrivaTran proposes the use of newly-developed manufacturing methods that convert materials commonly found in conventional integrated circuit (IC) manufacturing into memristor devices with increased packing density and an advanced, three-dimensional (3D) architecture. The memristor devices can be formed in the interconnect layers of a conventional IC so that the area available for underlying transistors is not affected. This approach results in a 3D architecture achieved using a single substrate without the need for bonding multiple die together with flip-chip or through-silicon-via technologies. Furthermore, the memristor devices are much smaller than single transistors for any given technology node, and will scale to smaller dimensions as IC technology continues to progress towards smaller and smaller transistor sizes. The two-terminal memristor devices have numerous advantages including on/off conductance ratios greater than 104, reversible and fast switching, long retention times and immunity to current-induced degradation. In addition, their inherent simplicity makes them highly compatible with Si-based microelectronics technology, leading to a 3D architecture that can be readily transferred into semiconductor products at the most basic, integrated circuit level.


Grant
Agency: NSF | Branch: Standard Grant | Program: | Phase: | Award Amount: 468.97K | Year: 2011

This Small Business Innovation Research (SBIR) Phase II project will further develop a two-terminal, electronically-programmable, nonvolatile memory array using materials commonly found in integrated circuit (IC) manufacturing. Each element is smaller than a single transistor and is formed using standard IC layers. This results in a three-dimensional (3D) integrated memory (3DIM) architecture achieved using a single substrate without need to assemble multiple die or wafers together with advanced bonding techniques. The ON/OFF conductance ratio and switching speed of these devices exceed the performance of competing technologies. Current flows through nanometer-sized regions of the device, and, as a result, the memory elements will scale to smaller dimensions without reducing the current through the device, thereby resulting in a dense memory array architecture with improved signal-to-noise ratio for each subsequent IC technology. The proposed overall program will include integrating a passivation layer, connecting each element with an isolation diode, optimizing device architecture to minimize footprint, and implementing 3DIM control and drive interface electronics. The program proposed herein addresses the topic by providing material innovations for improved performance in electronics where nano-scale semiconducting filaments are fabricated within a dielectric material for commercial data storage applications.

The broader impact/commercial potential of this project are in the areas of microelectronics chip manufacturing for wireless, mobile internet and other portable devices using nonvolatile memory. Memristive device arrays impact numerous commercial markets including flash and embedded memory, and offer orders of magnitude more density as compared to conventional memory. By implementing massively dense 3D memory array architecture on a single substrate, there is no need to fabricate multiple substrates and bond them together, thereby simplifying the fabrication process, reducing manufacturing cost and increasing yield. In addition to portable devices, the proposed device may find applications in space-based earth sciences and astronomy since it is tolerant to x-ray and heavy ion radiation. Some recent approaches to achieve 3D memory on a single substrate have not been successful due to problems with external fields causing bit errors and low signal-to-noise ratio, or because device operation is based on thermal, ionic transport, or phase-change mechanisms that are inherently slow. The proposed memory elements are controlled using electrical signals rather than thermal or chemical energy, making them highly efficient and faster than competing technologies. Memory arrays will be fabricated in a commercial foundry and scaled to smaller dimensions throughout the Phase II project.


Grant
Agency: Department of Defense | Branch: Navy | Program: SBIR | Phase: Phase II | Award Amount: 499.92K | Year: 2014

PrivaTran proposes to develop a semi-active laser (SAL) receiver read-out integrated circuit (ROIC) with interface to government furnished equipment (GFE) sensor arrays for advanced dual-band SAL receiver systems. Large-area focal plane array (FPA) technology and the PrivaTran ROIC provide high timing accuracy, use of both eye-hazardous and eye-safe lasers, precision guidance, improved weapons delivery accuracy, higher resistance to false targets, enhanced jammer discrimination, and increased overall weapon systems effectiveness while maintaining the same active area as conventional quad-cell systems in a low cost, strap down sensor design. The ROIC provides high-bandwidth sample-and-hold to capture pulse-shape data with enhanced resolution and high signal-to-noise ratio (SNR). The advanced sampling circuit allows pulses to be captured while simultaneously reading the data buffer, resulting in no sampling dead time. These features allow relative range imaging for improved discrimination of false targets such as fog, smoke and other reflections that can cause targeting errors in urban battle field conditions, leading to improved targeting, better friend-versus-foe identification, designator flexibility, and superior jammer resistance.


Grant
Agency: National Aeronautics and Space Administration | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 125.00K | Year: 2014

Integrated circuits in NASA spacecraft and Robotic Exploration Technologies that enable exploration of the solar system planets, moons and small bodies must operate over large temperature extremes and mitigate radiation effects that can result in upset or destruction of devices. Development of a reliable, high-performance nonvolatile memory (NVM) is critical to successful NASA explorations and development of robotic exploration technologies designed to operate in the extreme temperature, pressure and radiation environments of planetary and lunar surfaces. PrivaTran has previously demonstrated an electronically-programmable resistor as a NVM element. Initial static data retention testing has shown tolerance to several radiation types and high thermal stress, thereby demonstrating the potential for use in radiation-hardened circuits for extreme environments. Device materials and fabrication processes are compatible with high-temperature semiconductor manufacturing platforms utilizing wide-bandgap semiconductor materials. The PrivaTran NVM device uses standard materials as the active switching medium and device electrodes can be formed either in the substrate material or within the interconnect layers of the integrated circuit (IC). As a result, NVM arrays can be integrated with wide-band-gap semiconductor materials in a three-dimensional (3D) architecture, resulting in a high-density memory with superior NVM performance and significant savings in size, weight, power and cost.


Grant
Agency: National Science Foundation | Branch: | Program: SBIR | Phase: Phase II | Award Amount: 390.81K | Year: 2011

This Small Business Innovation Research (SBIR) Phase II project will further develop a two-terminal, electronically-programmable, nonvolatile memory array using materials commonly found in integrated circuit (IC) manufacturing. Each element is smaller than a single transistor and is formed using standard IC layers. This results in a three-dimensional (3D) integrated memory (3DIM) architecture achieved using a single substrate without need to assemble multiple die or wafers together with advanced bonding techniques. The ON/OFF conductance ratio and switching speed of these devices exceed the performance of competing technologies. Current flows through nanometer-sized regions of the device, and, as a result, the memory elements will scale to smaller dimensions without reducing the current through the device, thereby resulting in a dense memory array architecture with improved signal-to-noise ratio for each subsequent IC technology. The proposed overall program will include integrating a passivation layer, connecting each element with an isolation diode, optimizing device architecture to minimize footprint, and implementing 3DIM control and drive interface electronics. The program proposed herein addresses the topic by providing material innovations for improved performance in electronics where nano-scale semiconducting filaments are fabricated within a dielectric material for commercial data storage applications. The broader impact/commercial potential of this project are in the areas of microelectronics chip manufacturing for wireless, mobile internet and other portable devices using nonvolatile memory. Memristive device arrays impact numerous commercial markets including flash and embedded memory, and offer orders of magnitude more density as compared to conventional memory. By implementing massively dense 3D memory array architecture on a single substrate, there is no need to fabricate multiple substrates and bond them together, thereby simplifying the fabrication process, reducing manufacturing cost and increasing yield. In addition to portable devices, the proposed device may find applications in space-based earth sciences and astronomy since it is tolerant to x-ray and heavy ion radiation. Some recent approaches to achieve 3D memory on a single substrate have not been successful due to problems with external fields causing bit errors and low signal-to-noise ratio, or because device operation is based on thermal, ionic transport, or phase-change mechanisms that are inherently slow. The proposed memory elements are controlled using electrical signals rather than thermal or chemical energy, making them highly efficient and faster than competing technologies. Memory arrays will be fabricated in a commercial foundry and scaled to smaller dimensions throughout the Phase II project.


Grant
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase I | Award Amount: 149.96K | Year: 2012

ABSTRACT: PrivaTran will measure the radiation tolerance of new memristive materials and will design, model and simulate advanced memristor-based architectures for nonvolatile random access memory (RAM). The requirements for proper memory element isolation, programming voltage drive and current sense circuitry will be determined by circuit analysis. Memristor circuit models will be developed and used to trade different memristor types and optimize performance to the technical program objectives. Viable circuit topologies will be identified that enable high-density data storage solutions for aerospace and defense applications. Phase II prototype fabrication and commercialization work plans will be developed including a manufacturability analysis addressing materials compatibility and integration methods for insertion into current CMOS and BJT platforms as well as scaling the technology to the 10nm technology node and beyond. BENEFIT: The benefits of the proposed memristor architecture and materials include low-power nonvolatile memory operation, inherent radiation tolerance, good data retention over large temperature extremes, compatibility with three-dimensional (3D) memory architecture, fast switching speeds, large ON/OFF dynamic range, vacuum compatibility, highly-localized switching, good immunity to EMI, and unipolar switching, thus enabling a low-cost, high-density, memristor-based RAM that can be directly inserted into current and future Complementary Metal-Oxide-Semiconductor (CMOS) and Bipolar Junction Transistor (BJT) semiconductor manufacturing platforms to provide a solution for aerospace and defense systems with the combined performance of conventional hard disk, RAM and FLASH memory technology.


Grant
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase II | Award Amount: 750.00K | Year: 2013

ABSTRACT: PrivaTran will measure the radiation tolerance of new resistive memory materials and will design and fabricate advanced memristor-based architectures for nonvolatile random access memory (RAM) applications that are suitable for aerospace systems. The requirements for proper memory element isolation, programming voltage drive and current sense circuitry will be determined by circuit analysis. Prototype memristor-based memory arrays will be fabricated in a commercial semiconductor manufacturing foundry and radiation testing will be done to measure the radiation hardness of the design. Performance will be optimized to meet technical program objectives. Manufacturability and scalability will be investigated, and manufacturing process technologies will be identified that enable high-density data storage solutions for aerospace and defense applications. BENEFIT: The benefits of the proposed memristor architecture and materials include low-power nonvolatile memory operation, inherent radiation tolerance, good data retention over large temperature extremes, compatibility with three-dimensional (3D) memory architecture, fast switching speeds, large ON/OFF dynamic range, vacuum compatibility, highly-localized switching, good immunity to EMI, and unipolar switching, thus enabling a low-cost, high-density, memristor-based RAM that can be directly inserted into current and future Complementary Metal-Oxide-Semiconductor (CMOS) and Bipolar Junction Transistor (BJT) semiconductor manufacturing platforms to provide a solution for aerospace and defense systems with the combined performance of conventional hard disk, RAM and FLASH memory technology.

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