Kumamoto-shi, Japan
Kumamoto-shi, Japan

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Yoshikawa K.,Tohoku University | Yoshikawa K.,Apprecia Technology Inc. | Miyazaki T.,PRE Technology at CO. | Watanabe N.,Japan National Institute of Advanced Industrial Science and Technology | Aoyagi M.,Japan National Institute of Advanced Industrial Science and Technology
ECS Transactions | Year: 2012

We developed the high-speed alkaline etching of silicon for achieving backside exposure of through silicon vias (TSVs). The spin-etching rate of silicon was 2.1-6.6 μm/min when an accelerator was added to a KOH solution. The etching rate ratio of silicon to tetraethyl orthosilicate (TEOS) SiO 2 was 66-125. We also applied a KOH/accelerator solution to an 8-inch Si (100) wafer with buried Cu/Ta vias. The majority of buried Cu/Ta vias were uniformly exposed. Although terraced structures were generated on the Si surface, their step height was so small that it was negligible for practical purposes. © The Electrochemical Society.


Watanabe N.,Japan National Institute of Advanced Industrial Science and Technology | Miyazaki T.,PRE Technology at CO. | Aoyagi M.,Japan National Institute of Advanced Industrial Science and Technology | Yoshikawa K.,Tohoku University | Yoshikawa K.,Apprecia Technology Inc.
Proceedings of the 2012 IEEE 14th Electronics Packaging Technology Conference, EPTC 2012 | Year: 2012

In this study, we developed silicon wafer thinning and backside via exposure by wet etching for low-cost, damage-less through silicon via (TSV) formation. Silicon wafer thinning down to approximately 50 μm was carried out using a highly concentrated HF/HNO3 solution, and backside via exposure was carried out using an alkaline solution (accelerator-added KOH solution), without damaging the TSV liner oxide. The Si etching rates of these processes were 600-800 μm/min and 4 μm/min (at 75 °C), respectively. We also evaluated the damage to the silicon surface and TSV after these processes. The observations using an optical microscope, a transmission electron microscope (TEM), and a scanning electron microscope (SEM) showed that no damage layers were formed at the Si surface or TSVs. In addition, the leakage current between the TSVs was found to be very small. © 2012 IEEE.


Yoshikawa K.,Tohoku University | Yoshikawa K.,Pre Technology at Co. | Miyazaki T.,Pre Technology at Co. | Watanabe N.,Japan National Institute of Advanced Industrial Science and Technology | Aoyagi M.,Japan National Institute of Advanced Industrial Science and Technology
ECS Transactions | Year: 2012

We proposed the wet-chemical Si wafer-thinning process and evaluated the damage caused by this process. For the damage evaluation, we measured the die fracture stress and fracture energy, and compared various wafer-thinning processes (backgrinding, wet-chemical Si wafer-thinning, backgrinding + chemical mechanical polishing, backgrinding + wet etching). The result of comparative study shows that wet-chemical wafer-thinning processing has very high fracture stress/energy demonstrating that the damage of wet-chemical Si wafer-thinning process is very small. ©The Electrochemical Society.


Watanabe N.,Japan National Institute of Advanced Industrial Science and Technology | Miyazaki T.,PRE Technology at Co. | Yoshikawa K.,Tohoku University | Aoyagi M.,Japan National Institute of Advanced Industrial Science and Technology
IEEE Transactions on Components, Packaging and Manufacturing Technology | Year: 2014

To realize low-cost and damage-less through silicon via (TSV) formation, we evaluated the damage caused by a new wet-chemical Si-wafer thinning/backside via exposure process. Damage at the etched Si subsurface was examined using ball-on-ring tests, cross-sectional transmission electron microscopy, and electron energy loss spectroscopy. The die fracture load obtained after this process was higher than those for processes that include a backgrinding step. There was little damage to the etched Si subsurface layer after our new process. We then evaluated the damage in 0.8-μm metal-oxide-semiconductor field-effect transistor generated by the new process. The changes in threshold voltage, subthreshold swing, transconductance, and leakage current were very small, even when the wafer was thinned down to 20 μm. Finally, we applied our new process to a Cu/Ta via wafer to evaluate the damage in a TSV. No damaged layers were observed in the TSV, and the leakage current between the TSVs after this process was sufficiently small for practical application. © 2014 IEEE.


Watanabe N.,Japan National Institute of Advanced Industrial Science and Technology | Miyazaki T.,PRE Technology at Co. | Aoyagi M.,Japan National Institute of Advanced Industrial Science and Technology | Yoshikawa K.,PRE Technology at Co.
Proceedings - Electronic Components and Technology Conference | Year: 2012

We evaluated the damage of an etched silicon surface after the wet-chemical silicon-wafer thinning process. The damage evaluation was carried out by cross-sectional transmission electron microscope (TEM) observation/electron energy-loss spectroscopy (EELS) analysis of the etched surface and measurement of die fracture stress. The results of the TEM observation/EELS analysis indicated the absence of damage layers. The three-point bending test showed that this process offered a higher die fracture stress than other processes including backgrinding. We also applied this process to thinning of the CMOS wafer and measured the change in the MOSFET characteristics. The change in MOSFET characteristics was found to be very small even when the CMOS wafer was thinned to 50 μm. © 2012 IEEE.


Watanabe N.,Japan National Institute of Advanced Industrial Science and Technology | Miyazaki T.,PRE Technology at Co. | Aoyagi M.,Japan National Institute of Advanced Industrial Science and Technology | Yoshikawa K.,PRE Technology at Co.
2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 | Year: 2011

We evaluate the surface damage caused by the wet-chemical wafer-thinning process by measuring the die fracture stress. The die fracture stress afforded by this process is higher than those afforded by other methods including backgranding. In addition, we investigate the impact of residual stress, generated by the wet-chemical wafer-thinning process, on MOSFET operations. It is found that the change in MOSFET characteristics is very small, even when the wafer is thinned down to 50 μm. © 2011 IEEE.

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