Powerchip Semiconductor Corporation

Hsinchu, Taiwan

Powerchip Semiconductor Corporation

Hsinchu, Taiwan

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Chen C.-M.,Powerchip Semiconductor Corporation | Yeh M.-H.,Powerchip Semiconductor Corporation | Chien H.-J.,Powerchip Semiconductor Corporation | Fan J.-J.,Powerchip Semiconductor Corporation | And 2 more authors.
Microelectronic Engineering | Year: 2010

In this paper, we demonstrate that vacuum ultraviolet (VUV) irradiation was effective to promote the wet etch resistance of perhydro-polysilazane-based inorganic spin-on-glass (PSZ-SOG) film inside the gap. The baking condition of VUV irradiation was chosen at 150 °C in 0.2 Pa before furnace curing process. Observed the densification characteristics of various trench sizes (aspect ratio (AR) = 3.1-0.13), all densification coefficient (D eff) of the samples with VUV irradiation were larger than 0.90. On the contrary, for the sample without VUV irradiation, a remarkable reduction of D eff values from 0.99 to 0.58 was found while the AR increasing from 0.13 to 3.1. The better densification characteristics of PSZ-SOG films were mainly contributed to the VUV photon. Compared with the reaction mechanisms during VUV irradiation and furnace curing, VUV photon is responsible for triggering the Si-N bond dissociation and accelerating the conversion rate of PSZ. Finally, the new reaction mechanism makes SOG films denser at STI region without additional thermal budget. © 2009 Elsevier B.V. All rights reserved.


Ho C.-Y.,Chung Yuan Christian University | Lin X.J.,Powerchip Semiconductor Corporation | Chien H.R.,Powerchip Semiconductor Corporation | Lien C.,National Tsing Hua University
Thin Solid Films | Year: 2010

In this study, a high aspect ratio contact pattern, beyond 70 nm technology, in a very-large-scale integrated circuit, was achieved using hydrogenated amorphous carbon (a-C:H) film as the dry etching hard mask. The effect of temperature on the a-C:H deposits prepared by plasma enhanced chemical vapor deposition was studied. The a-C:H films resulting from propylene (C 3H6) decomposition exhibited high transparency incorporated rich hydrogen concentration with a decreasing deposition temperature. A matrix of dispersed cross-linked sp3 clusters in a-C:H films, which has an increasing optical band gap and higher hydrogen content, is attributed to reduce the defect density of status and obtain high transmittance rate. Moreover, the higher transparency of a-C:H films could afford lithographic aligned capability as well as compressive stress and dry etching resistance. These explorations provided insights into the role of hydrogen in a-C film and also into the practicality of its future nano-scale device applications. © 2010 Elsevier B.V. All rights reserved.


Ho C.Y.,National Taiwan University | Shih K.-Y.,Powerchip Semiconductor Corporation | He J.H.,National Taiwan University
Microelectronic Engineering | Year: 2010

The phenomenon of floating gate (FG) crystallization and extrinsic gate oxide breakdown (Vbd) are discussed using polysilazane-base inorganic material SOD (Spin-On-Dielectric) as shallow trench isolation (STI) filling for 50 nm flash memory fabrication. The pinholes are found along the FG grain boundary in wide active regions because of tensile stress induced by SOD material in STI process, thus gate oxide wears out by following wet cleaning steps. The chemical oxide formation during FG deposition can effectively inhibit gate oxide early breakdown. Moreover, FG sheet resistance (Rs) in 550 °C/air deposition condition can significantly reduce about 20% in comparison with 520 °C/O2 and 400 °C/N2 conditions. © 2009 Elsevier B.V. All rights reserved.


Chang Y.-S.,Powerchip Semiconductor Corporation | Sweis J.,Cadence Design Systems Inc. | Lai J.-C.,Powerchip Semiconductor Corporation | Lin C.-C.,Powerchip Semiconductor Corporation | Yu J.,Cadence Design Systems Inc.
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2010

Self Aligned Double Patterning (SADP) has the advantage of dense array definition with good pitch control and is hence useful for memory devices; but its feasibility of two-dimensional circuit patterns definition is restricted on the other hand. In SPIE 2009, we had proposed the ideas of 30nm node NAND FLASH cell circuit critical feature (pickup, gate, contact array) decomposition by SADP, based on manual design. The concerns of process integration as well as SADP alignment algorithm for each mask step were investigated and countermeasures were presented. In this paper, the previous works on manual-based pattern decomposition are extended to a more sophisticated use on full-area NAND FLASH critical layer layout decomposition by utilizing an automated electronic design (EDA) tool. The decomposition tool together with OPC and simulation tools are integrated to optimize the lithographic performance of local critical patterns in each decomposed mask step, and comparisons have been made as well to investigate the differences in layout splitting algorithm between EDA-based and manual-based decomposition. Finally, the full-area (9350x12800um) layout decomposition has been successfully demonstrated on NAND FLASH Gate and Metal critical layers by using the EDA tool with improved 2D structure handling algorithms. © 2010 Copyright SPIE - The International Society for Optical Engineering.


Yeh S.-S.,Powerchip Semiconductor Corporation | Zhu A.,Cadence Design Systems Inc. | Chen J.,Cadence Design Systems Inc. | Yenikaya B.,Cadence Design Systems Inc. | And 2 more authors.
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2014

It's critical to address the yield issues caused by process specific layout patterns with limited process window. RETs such as PWOPC are introduced to guarantee high lithographic margin, but these techniques cost high run-time when applied to full-chips. There's also lack of integrated solution to easily identify, define comprehensive patterns and apply different controls and/or constraints over these patterns through different stages of OPC/RET process. In this paper, we study a pattern aware OPC flow that applies PWOPC or specific corrections locally to layouts with critical and yield limiting patterns. Although the full chip PWOPC provides an effective way, it causes great amount of run time penalty and does not achieve optimal process window. Overall, PAOPC achieves the better margins over the hotspots, without sacrificing turnaround time. The study demonstrates the benefit of the new flow with fine grained process window controls over different patterns. This flow get good improvement on defect counts when evaluated on 50 nm node logic devices. © 2014 SPIE.


Lin Y.-C.,Powerchip Semiconductor Corporation | Chang H.-J.,Powerchip Semiconductor Corporation
Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA | Year: 2010

In the studies, we investigate the cause of failure that occur during pilot run and new process evaluation. The results are fed back to wafer and assembly design and process improvement. From our results, the evaluation for package qualification can find out not only package but also wafer process issue. © 2010 IEEE.


Lin W.P.,Powerchip Semiconductor Corporation | Chang H.J.,Powerchip Semiconductor Corporation
Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA | Year: 2010

As the device feature size smaller and circuit complexity increase rapidly, failure analysis techniques to isolate defects will become more difficult and challenging. In this work, The new technique which combine EBAC/EBIC and nano-probing in a SEM system is presented. We study the new technique for failure site location and report two FA cases. One is 70 nm gate oxide thinner by AEI model and another is 65nm device damaged by two probes VDIC model. We conclude that this technology provides us an effective alternative solution for semiconductor failure analysis. © 2010 IEEE.


Patent
POWERCHIP SEMICONDUCTOR Corporation | Date: 2011-08-26

A phase change memory device is provided, including a substrate, a first dielectric layer disposed over the substrate, a first electrode disposed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer, covering the first electrode, a heating electrode disposed in the second dielectric layer, contacting the first electrode, a phase change material layer disposed over the second dielectric layer, contacting the heating electrode, and a second electrode disposed over the phase change material layer. In one embodiment, the heating electrode includes a first portion contacting the first electrode and a second portion contacting the phase change material layer, and the second portion of the heating electrode includes metal silicides and the first portion of the heating electrode includes no metal silicides.


Patent
POWERCHIP SEMICONDUCTOR Corporation | Date: 2011-11-23

A method for forming a phase change memory device is disclosed. A substrate with a bottom electrode thereon is provided. A heating electrode and a dielectric layer are formed on the bottom electrode, wherein the heating electrode is surrounded by the dielectric layer. The heating electrode is etched to form recess in the dielectric layer. A phase change material is deposited on the dielectric layer, filling into the recess. The phase change material is polished to remove a portion of the phase change material exceeding the surface of the dielectric layer and a phase change layer is formed confined in the recess of the dielectric layer. A top electrode is formed on the phase change layer and the dielectric layer.


Patent
POWERCHIP SEMICONDUCTOR Corporation | Date: 2010-11-05

Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a bottom electrode formed over a substrate. A first dielectric layer is formed over the bottom electrode. A heating electrode is formed in the first dielectric layer and partially protrudes over the first dielectric layer, wherein the heating electrode includes an intrinsic portion embedded within the first dielectric layer, a reduced portion stacked over the intrinsic portion, and an oxide spacer surrounding a sidewall of the reduced portion. A phase change material layer is formed over the first dielectric layer and covers the heating electrode, the phase change material layer contacts a top surface of the reduced portion of the heating electrode. A top electrode is formed over the phase change material layer and contacts the phase change material layer.

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