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Ho C.Y.,National Taiwan University | Shih K.-Y.,Powerchip Semiconductor Corporation | He J.H.,National Taiwan University
Microelectronic Engineering | Year: 2010

The phenomenon of floating gate (FG) crystallization and extrinsic gate oxide breakdown (Vbd) are discussed using polysilazane-base inorganic material SOD (Spin-On-Dielectric) as shallow trench isolation (STI) filling for 50 nm flash memory fabrication. The pinholes are found along the FG grain boundary in wide active regions because of tensile stress induced by SOD material in STI process, thus gate oxide wears out by following wet cleaning steps. The chemical oxide formation during FG deposition can effectively inhibit gate oxide early breakdown. Moreover, FG sheet resistance (Rs) in 550 °C/air deposition condition can significantly reduce about 20% in comparison with 520 °C/O2 and 400 °C/N2 conditions. © 2009 Elsevier B.V. All rights reserved. Source


Patent
POWERCHIP SEMICONDUCTOR Corporation | Date: 2011-08-26

A phase change memory device is provided, including a substrate, a first dielectric layer disposed over the substrate, a first electrode disposed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer, covering the first electrode, a heating electrode disposed in the second dielectric layer, contacting the first electrode, a phase change material layer disposed over the second dielectric layer, contacting the heating electrode, and a second electrode disposed over the phase change material layer. In one embodiment, the heating electrode includes a first portion contacting the first electrode and a second portion contacting the phase change material layer, and the second portion of the heating electrode includes metal silicides and the first portion of the heating electrode includes no metal silicides.


Patent
POWERCHIP SEMICONDUCTOR Corporation | Date: 2011-11-23

A method for forming a phase change memory device is disclosed. A substrate with a bottom electrode thereon is provided. A heating electrode and a dielectric layer are formed on the bottom electrode, wherein the heating electrode is surrounded by the dielectric layer. The heating electrode is etched to form recess in the dielectric layer. A phase change material is deposited on the dielectric layer, filling into the recess. The phase change material is polished to remove a portion of the phase change material exceeding the surface of the dielectric layer and a phase change layer is formed confined in the recess of the dielectric layer. A top electrode is formed on the phase change layer and the dielectric layer.


Ho C.-Y.,Chung Yuan Christian University | Lin X.J.,Powerchip Semiconductor Corporation | Chien H.R.,Powerchip Semiconductor Corporation | Lien C.,National Tsing Hua University
Thin Solid Films | Year: 2010

In this study, a high aspect ratio contact pattern, beyond 70 nm technology, in a very-large-scale integrated circuit, was achieved using hydrogenated amorphous carbon (a-C:H) film as the dry etching hard mask. The effect of temperature on the a-C:H deposits prepared by plasma enhanced chemical vapor deposition was studied. The a-C:H films resulting from propylene (C 3H6) decomposition exhibited high transparency incorporated rich hydrogen concentration with a decreasing deposition temperature. A matrix of dispersed cross-linked sp3 clusters in a-C:H films, which has an increasing optical band gap and higher hydrogen content, is attributed to reduce the defect density of status and obtain high transmittance rate. Moreover, the higher transparency of a-C:H films could afford lithographic aligned capability as well as compressive stress and dry etching resistance. These explorations provided insights into the role of hydrogen in a-C film and also into the practicality of its future nano-scale device applications. © 2010 Elsevier B.V. All rights reserved. Source


Lin Y.-C.,Powerchip Semiconductor Corporation | Chang H.-J.,Powerchip Semiconductor Corporation
Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA | Year: 2010

In the studies, we investigate the cause of failure that occur during pilot run and new process evaluation. The results are fed back to wafer and assembly design and process improvement. From our results, the evaluation for package qualification can find out not only package but also wafer process issue. © 2010 IEEE. Source

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