San Jose, CA, United States
San Jose, CA, United States

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Patent
Power Integrations Inc. | Date: 2017-03-22

A boost-bypass converter includes a boost inductor coupled between an input and an output of the boost-bypass converter. A bypass diode is coupled between the input the output of the boost-bypass converter. A boost switching element is coupled to the boost inductor, and is coupled to be activated during a first interval in each line half cycle of an input voltage to boost an output voltage at the output of the boost-bypass converter. The boost switching element is coupled to be deactivated during a second interval in said each line half cycle such that the output voltage drops towards the input voltage. The output voltage is coupled to follow the input voltage during a third interval in said each line half cycle of the input voltage. Energy is transferred between the input and the output of the boost-bypass converter through the bypass diode during the third interval.


Patent
Power Integrations Inc. | Date: 2017-02-15

A diode includes a two-dimensional electron gas formed in a heterojunction defined between first and second semiconductor material layers. First and second layers of insulating material are disposed on the second semiconductor layer. First and second electrodes are disposed in the second layer of insulating material. The first electrode is coupled to the second semiconductor material layer. The second electrode is coupled to the heterojunction. Third and fourth layers of insulating material are disposed on the second insulating layer. A first via is disposed in the fourth layer of insulating material and coupled to the second electrode. A first field plate is disposed in the fourth layer of insulating material. An edge of the first field plate laterally extends towards first via. The first via is separated from an edge of the first via. The first field plate is coupled to the first electrode.


Patent
Power Integrations Inc. | Date: 2016-12-22

A semiconductor device includes a substrate and a first active layer disposed over the substrate. The semiconductor device also includes a second active layer disposed on the first active layer such that a lateral conductive channel arises between the first active layer and the second active layer. a source, gate and drain contact are disposed over the second active layer. A conductive charge distribution structure is disposed over the second active layer between the gate and drain contacts. The conductive charge distribution structure is capacitively coupled to the gate contact.


Switches comprising a normally-off semiconductor device and a normally-on semiconductor device in cascode arrangement are described. The switches include a capacitor connected between the gate of the normally-on device and the source of the normally-off device. The switches may also include a zener diode connected in parallel with the capacitor between the gate of the normally-on device and the source of the normally-off device. The switches may also include a pair of zener diodes in series opposing arrangement between the gate and source of the normally-off device. Switches comprising multiple normally-on and/or multiple normally-off devices are also described. The normally-on device can be a JFET such as a SiC JFET. The normally-off device can be a MOSFET such as a Si MOSFET. The normally-on device can be a high voltage device and the normally-off device can be a low voltage device. Circuits comprising the switches are also described.


Patent
Power Integrations Inc. | Date: 2016-12-21

Devices are disclosed for providing heterojunction field effect transistor (HFETs) having improved performance and/or reduced noise generation. A gate electrode is over a portion of the active region and is configured to modulate a conduction channel in the active region of an HFET. The active region is in a semiconductor film between a source electrode and a drain electrode. A first passivation film is over the active region. An encapsulation film is over the first passivation film. A first metal pattern on the encapsulation film includes a shield wrap over the majority of the active region and is electrically connected to the source electrode


A method of operating a power converter includes applying a first signal sequence to one or more terminals of the power converter to unlock a controller of the power converter and cause the controller to enter a programming mode, applying a second signal sequence to the one or more terminals of the power converter to program a controller parameter of the power converter, and applying a third signal sequence to the one or more terminals to lock the controller of the power converter and cause the power converter to enter a locked mode. The one or more terminals of the power converter includes one or more input terminals of the power converter that converter are adapted to be coupled to a programmable ac or dc supply, or one or more output terminals of the power converter that are adapted to be coupled to a programmable electronic load.


Patent
Power Integrations Inc. | Date: 2016-09-14

A transformer for use in a power converter includes a first winding including a plurality of layers wound around a magnetic core. A first exclusionary winding is wound around the magnetic core forming a first exclusionary winding layer. A first section of the plurality of layers of the first winding is wound closer to a center of the magnetic core than the first exclusionary winding layer. A second exclusionary winding is wound around the magnetic core forming a second exclusionary winding layer. The first and second exclusionary windings have an equal number of turns around the magnetic core. A second section of the plurality of layers of the first winding is wound around the magnetic core between the first exclusionary winding layer and the second exclusionary winding layer.


Patent
Power Integrations Inc. | Date: 2017-03-03

A semiconductor device includes a substrate and a first active layer disposed over the substrate. The semiconductor device also includes a second active layer disposed on the first active layer such that a lateral conductive channel arises between the first active layer and the second active layer a source, gate and drain contact are disposed over the second active layer. A conductive charge distribution structure is disposed over the second active layer between the gate and drain contacts. The conductive charge distribution structure is capacitively coupled to the gate contact.


Patent
Power Integrations Inc. | Date: 2017-03-06

A controller for use in a power converter includes a first terminal to provide a turn on signal to initiate turning on of a power switch and a second terminal to provide a turn off signal to initiate turning off the power switch. A detection circuit is coupled to detect a turn off time delay. The turn off time delay is the duration of time between an initiating of a turn off of the power switch by the turn off signal and an actual turn off of the power switch. A control circuit is coupled to control the turn on signal to regulate the turn off delay time to a target time value. The control circuit controls the turn on signal by controlling an amount of charge delivered to turn on the power switch.


A controller for use in a power converter includes an initialization circuit coupled to a sense terminal coupled to an external resistor to receive a sense voltage from external resistor during a startup mode of the power converter. The sense terminal is coupled to sense an output current of the power converter after the startup mode of the power converter is complete. A decoder circuit is coupled to receive the sense voltage from the initialization circuit during the startup mode of the power converter. The decoder circuit is coupled to sense a voltage across an external resistor during the startup mode of the power converter to determine a value of the external resistor to set an operating parameter of the power converter in response to the value of the external resistor.

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