Santa Clara, CA, United States
Santa Clara, CA, United States

PMC-Sierra is an American fabless semiconductor company which develops and sells devices into the communications, storage, printing, and embedded computing marketplaces. Wikipedia.


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Patent
PMC-Sierra | Date: 2015-12-17

A power-saving method and circuit in a data processing device comprising a data buffer. Read commands associated with a data source and a data destination are received at the data processing device. The read commands are accumulated until an amount of read data associated with the read commands is greater than a predefined threshold. When the amount of read data is less than the predefined threshold and the data buffer is empty, the data buffer is signaled to enter or to maintain a sleep mode. When the amount of read data is at least the predefined threshold, the data buffer is signaled to exit the sleep mode following a preconfigured delay. Processing of the read commands and read data in respective pipelines is monitored to time exiting of the buffer from the sleep mode for arrival of the read data. Sleep mode use and thus power saving are optimized.


A solid-state storage device (SSD) controller is provided for use with an SSD. The SSD includes a plurality of memory cells, such as non-volatile memory (NVM) cells. The SSD controller comprises a processor and a memory storing statements and instructions for execution by the processor to perform a method of configuring the memory cells. In a dynamic configuration implementation in which at least a subset of the NVM cells are configured in a first NVM storage mode, the method includes: monitoring data activity in relation to the SSD; and dynamically reconfiguring the subset of the NVM cells in a second bit retention mode based on the monitored data activity. In a static configuration implementation, the method includes receiving at least one performance characteristic for the NVM cells; and configuring the subset of the NVM cells in a first bit retention mode based on the received at least one performance characteristic.


Patent
PMC-Sierra | Date: 2014-01-30

A random noise generation module for generating noisy LLRs for testing an error correction circuit of a nonvolatile memory storage module. The random noise generation module includes a coefficient generator for generating one or a plurality of coefficients, each of the plurality of coefficients associated with one region of a plurality of regions defining a linear space proportionately divided according to an area under a probability distribution curve for a nonvolatile memory storage module. The random noise generation module further includes a linear random number generator for generating a linear random number and a comparator for comparing the linear random number to one or more of the plurality of coefficients to identify the region of the plurality of regions of the probability distribution curve in which the linear random number belongs to generate a noisy LLR for testing an error correction circuit of a nonvolatile memory storage module.


A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword. The controller further includes a plurality of neighboring cell contribution LLR look-up tables representative of the contribution of the neighboring cells to threshold voltage distribution of the memory storage module. The controller provides the LLRs from the appropriate LLR look-up table to an LDPC decoder for the subsequent decoding of the codeword.


A nonvolatile memory storage controller for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes partitioning circuitry for identifying a set of soft-decision reference voltages having the smallest calculated introduced error value based upon the estimated BER of the nonvolatile memory. The controller further includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using the set of soft-decision reference voltages having the smallest calculated LLR introduced error value to provide a plurality of soft-decision bits representative of the codeword. The controller further includes an LLR look-up table accessible by the read circuitry to provide LLRs to the LDPC decoder for the subsequent decoding of the codeword.


A system and method reading, accumulating and processing soft information for use in LDPC decoding. In accordance with the present invention, an LDPC decoder includes accumulation circuitry to receive soft reads of a cell of the nonvolatile memory storage module and to produce an accumulated soft read that can be used to identify an appropriate LLR for the cell. The accumulation circuitry of the present invention may include, an accumulation RAM, an arithmetic logic unit (ALU) and a soft accumulation control and sequencing module for accumulating and processing soft information for use in LDPC decoding.


An unrolled decision feedback equalizer (DFE) as disclosed herein has a reduced number of compensation factors while keeping a suitable performance level for a given application. The K^(N )possible DFE correction levels are reduced or compressed into fewer levels (R), merging together the levels that are the closest together where K represents the number of possible symbols in each baud, or the number of bits encoded into each baud, and N represents the DFE depth in number of bauds. A mapping function is then provided to convert the K^(N )combinations of previous history bits into R sampler selections.


A nonvolatile memory system and a method for using programming time to reduce bit errors in the nonvolatile memory system are disclosed. The method includes programming a plurality of memory cells of a nonvolatile memory device, identifying weak cells using programming time and preventing subsequent programming to the identified weak cells.


A SAS (Serial Attached SCSI or Serial Attached Small Computer System Interface) switch includes a master SAS expander and a multitude of slave expanders connected to the master SAS expander. Each slave expander has a distinct SAS address. The slave expanders are not directly connected to one another and communicate through the master expander. The SAS switch has a pair of SAS wide ports each having a multitude of SAS links each associated with one of the slave expanders. The slave expanders are configured to route SAS traffic in accordance with routing tables established by the master SAS expander. The master SAS expander is not directly connected to either of the SAS wide ports.


A processor-implemented method and integrated circuit package are provided. According to an implementation, a method of producing a chip package includes de-populating solder balls at selected locations in a fine pitch package, and providing test pads at the de-populated solder ball locations. In an example implementation, the method comprises receiving and modifying a package design. In an implementation, a row of test pads in an integrated circuit package is provided in a plurality of concentric annular rows, the row of test pads being adjacent an outer row of via-connected solder balls and adjacent an inner row of via-connected solder balls. In an implementation, test pads are located on a PCB-facing surface of the package at a subset of locations opposing at least one via position on a package-facing surface of the PCB. The test pads maintain a large number of signal pins and do not interfere with the via.

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