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Swindon, United Kingdom

Rae K.,University of Strathclyde | Xie E.Y.,University of Strathclyde | Trindade A.J.,University of Strathclyde | Guilhabert B.,University of Strathclyde | And 10 more authors.
2015 IEEE Photonics Conference, IPC 2015 | Year: 2015

We demonstrate an integrated dual-color InGaN light-emitting diode (LED) array by transfer printing blue LED structures from their silicon growth substrate in between the pixels of a pre-processed green LED array on a sapphire substrate. © 2015 IEEE. Source


Baine P.,Queens University of Belfast | Montgomery J.H.,Queens University of Belfast | Armstrong B.M.,Queens University of Belfast | Gamble H.S.,Queens University of Belfast | And 6 more authors.
IEEE Transactions on Electron Devices | Year: 2014

The buried oxide (BOX) layer in silicon on insulator (SOI) was replaced by a compound buried layer (CBL) containing layers of SiO2, polycrystalline silicon (polysilicon), and SiO2. The undoped polysilicon in the CBL acted as a dielectric with a higher thermal conductivity than SiO2. CBL provides a reduced thermal resistance with the same equivalent oxide thickness as a standard SiO2 buried layer. Thermal resistance was further reduced by lateral heat flow through the polysilicon. Reduction in thermal resistance by up to 68% was observed, dependent on polysilicon thickness. CBL SOI substrates were designed and manufactured to achieve a 40% reduction in thermal resistance compared with an 1.0-μm SiO2 BOX. Power bipolar transistors with an active silicon layer thickness of 13.5 μm manufactured on CBL SOI substrates showed a 5%-17% reduction in thermal resistance compared with the standard SOI. This reduction was dependent on transistor layout geometry. Between 65% and 90% of the heat flow from these power transistors is laterally through the thick active silicon layer. Analysis confirmed that CBL SOI provided a 40% reduction in the vertical path thermal resistance. Devices employing thinner active silicon layers will achieve the greater benefit from reduction in vertical path thermal resistance offered by CBL SOI. © 1963-2012 IEEE. Source


Connor S.,Plessey Semiconductors Ltd.
Sensors (Peterborough, NH) | Year: 2011

The electric potential integrated circuit (EPIC) sensor, an extremely robust solid-state electrometer with such high input impedance that it is close to being a perfect voltmeter, is presented. The electrode is protected by a capping layer of dielectric material to ensure that the electrode is isolated from the body being measured. The device is AC coupled with a lower corner frequency (-3dB) of a few tens of MHz and an upper corner frequency above 200 MHz. The device in single-ended mode can be used to read electric potential. The size of the electrode is somewhat arbitrary and depends on the input capacitance required for a particular application. The input capacitance can be driven as low as 10 -17 F with the input resistance being boosted to values up to around 10 15, thus keeping the interaction with the target field to an absolute minimum and ensuring that all currents are small displacement currents only. Source


Hakim M.M.A.,University of Southampton | Tan L.,University of Liverpool | Abuelgasim A.,University of Southampton | Mallik K.,University of Southampton | And 6 more authors.
IEEE Transactions on Electron Devices | Year: 2010

We report for the first time a CMOS-compatible silicidation technology for surround-gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for silicidation and is successfully integrated with a Fillet Local OXidation (FILOX) process, which thereby delivers low overlap capacitance and high-drive-current vertical devices. Silicided 80-nm vertical n-channel devices fabricated using 0.5-μm lithography are compared with nonsilicided devices. A sourcedrain (S/D) activation anneal of 30 s at 1100 °C is shown to deliver a channel length of 80 nm, and the silicidation gives a 60% improvement in drive current in comparison with nonsilicided devices. The silicided devices exhibit a subthreshold slope (S) of 87 mV/dec and a drain-induced barrier lowering (DIBL) of 80 mV/V, compared with 86 mV/dec and 60 mV/V for nonsilicided devices. S-parameter measurements on the 80-nm vertical nMOS devices give an f T of 20 GHz, which is approximately two times higher than expected for comparable lateral MOSFETs fabricated using the same 0.5-μ m lithography. Issues associated with silicidation down the pillar sidewall are investigated by reducing the activation anneal time to bring the silicided region closer to the p-n junction at the top of the pillar. In this situation, nonlinear transistor turn-on is observed in drain-on-top operation and dramatically degraded drive current in source-on-top operation. This behavior is interpreted using mixed-mode simulations, which show that a Schottky contact is formed around the perimeter of the pillar when the silicided contact penetrates too close to the top S/D junction down the side of the pillar. © 2006 IEEE. Source


Trindade A.J.,University of Strathclyde | Guilhabert B.,University of Strathclyde | Xie E.Y.,University of Strathclyde | Ferreira R.,University of Strathclyde | And 10 more authors.
Optics Express | Year: 2015

We report the transfer printing of blue-emitting micron-scale light-emitting diodes (micro-LEDs) onto fused silica and diamond substrates without the use of intermediary adhesion layers. A consistent Van der Waals bond was achieved via liquid capillary action, despite curvature of the LED membranes following release from their native silicon growth substrates. The excellence of diamond as a heat-spreader allowed the printed membrane LEDs to achieve optical power output density of 10 W/cm2 when operated at a current density of 254 A/cm2. This high-currentdensity operation enabled optical data transmission from the LEDs at 400 Mbit/s. © 2015 Optical Society of America. Source

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