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CHANDLER, Ariz., May 10, 2017 (GLOBE NEWSWIRE) -- The newest family of PIC32 microcontrollers (MCUs) is now available from Microchip Technology Inc. (NASDAQ:MCHP). The PIC32MK family features four highly integrated MCUs for precision dual Motor Control applications (PIC32MK MC) and eight MCUs packed with serial communication modules for General Purpose applications (PIC32MK GP). All MC and GP devices feature a 120 MHz 32-bit core that supports Digital Signal Processor (DSP) instructions. Additionally, to ease control algorithm development, a double-precision floating point unit is integrated into the MCU core enabling customers to utilize floating-point based modeling and simulation tools for code development. For more information about Microchip’s PIC32MK family visit: www.microchip.com/pic32mk. To increase efficiency and decrease the number of discrete devices needed in motor control applications, the high-performance PIC32MK MC devices combine 32-bit processing with advanced analog peripherals such as a quad 10 MHz op amp, high-speed comparators and motor-control optimized Pulse Width Modulation (PWM) modules. The devices also have Analog-to-Digital Converter (ADC) modules capable of total throughput of 25.45 Mega-Samples Per Second (MSPS) in 12-bit mode or 33.79 MSPS in 8-bit mode, enabling higher precision in motor control applications. The devices come with up to 1 MB Live Update Flash, 4 KB of EEPROM and 256 KB SRAM. “The PIC32MK family represents a continuation in the Microchip motor control lineup enabling traditional 8- and 16-bit customers to move to a 32-bit MCU for motor control while maintaining support through classic Microchip development tools,” said Rod Drake, vice president of Microchip’s MCU32 business unit. “The family also has general purpose MCUs with an extensive array of serial communications modules ideally suited for the industrial space.” With class-leading connectivity integration, the PIC32MK devices have up to four independent CAN 2.0 ports as well as six Universal Asynchronous Receiver/Transmitter (UART) modules, Local Interconnect Network (LIN) 1.2 and six Serial Peripheral Interface (SPI) or Inter-IC Sound (I2S) modules. Additionally, two complete full-speed USB modules are included on select devices enabling simultaneous USB host and USB device to be active at the same time.  A single MCU can be used to communicate to multiple bus protocols for reduced design complexity and cost, making PIC32MK devices ideal for dual-USB applications such as digital audio or CAN-based implementations in the automotive and industrial markets. Development Support As with all PIC32 devices, the PIC32MK family is supported by Microchip’s MPLAB® Harmony Integrated Software Framework, MPLAB X Integrated Development Environment (IDE), MPLAB XC32 Compiler for PIC32, MPLAB ICD 3 In-Circuit Debugger and MPLAB REAL ICE™ In-Circuit Emulation system. Several additional tools are available including: The PIC32MK devices have peripheral block support for MathWorks® MATLAB® and Simulink® as well as open-source-based Scilab® for customers interested in numerical computation computing environments for engineering and scientific applications. Pricing and Availability Devices in the PIC32MK family are offered with up to 1 MB Flash and 256 KB SRAM in 64- and 100-pin TQFP and QFN packaging options. All devices are available today in volume production starting at $4.50 in 10K quantities.             For additional information, contact any Microchip sales representative or authorized worldwide distributor. To purchase products mentioned in this press release, go to Microchip’s easy-to-use online sales channel microchipDIRECT or contact one of Microchip’s authorized distribution partners. Resources High-res images available through Flickr or editorial contact (feel free to publish): About Microchip Technology Microchip Technology Inc. (NASDAQ:MCHP) is a leading provider of microcontroller, mixed-signal, analog and Flash-IP solutions, providing low-risk product development, lower total system cost and faster time to market for thousands of diverse customer applications worldwide.  Headquartered in Chandler, Arizona, Microchip offers outstanding technical support along with dependable delivery and quality.  For more information, visit the Microchip website at www.microchip.com. Note:  The Microchip name and logo, the Microchip logo, PIC and MPLAB are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. REAL ICE is a trademark of Microchip Technology Inc. in the U.S.A. and other countries.  All other trademarks mentioned herein are the property of their respective companies.


CHANDLER, Ariz., May 10, 2017 (GLOBE NEWSWIRE) -- The newest family of PIC32 microcontrollers (MCUs) is now available from Microchip Technology Inc. (NASDAQ:MCHP). The PIC32MK family features four highly integrated MCUs for precision dual Motor Control applications (PIC32MK MC) and eight MCUs packed with serial communication modules for General Purpose applications (PIC32MK GP). All MC and GP devices feature a 120 MHz 32-bit core that supports Digital Signal Processor (DSP) instructions. Additionally, to ease control algorithm development, a double-precision floating point unit is integrated into the MCU core enabling customers to utilize floating-point based modeling and simulation tools for code development. For more information about Microchip’s PIC32MK family visit: www.microchip.com/pic32mk. To increase efficiency and decrease the number of discrete devices needed in motor control applications, the high-performance PIC32MK MC devices combine 32-bit processing with advanced analog peripherals such as a quad 10 MHz op amp, high-speed comparators and motor-control optimized Pulse Width Modulation (PWM) modules. The devices also have Analog-to-Digital Converter (ADC) modules capable of total throughput of 25.45 Mega-Samples Per Second (MSPS) in 12-bit mode or 33.79 MSPS in 8-bit mode, enabling higher precision in motor control applications. The devices come with up to 1 MB Live Update Flash, 4 KB of EEPROM and 256 KB SRAM. “The PIC32MK family represents a continuation in the Microchip motor control lineup enabling traditional 8- and 16-bit customers to move to a 32-bit MCU for motor control while maintaining support through classic Microchip development tools,” said Rod Drake, vice president of Microchip’s MCU32 business unit. “The family also has general purpose MCUs with an extensive array of serial communications modules ideally suited for the industrial space.” With class-leading connectivity integration, the PIC32MK devices have up to four independent CAN 2.0 ports as well as six Universal Asynchronous Receiver/Transmitter (UART) modules, Local Interconnect Network (LIN) 1.2 and six Serial Peripheral Interface (SPI) or Inter-IC Sound (I2S) modules. Additionally, two complete full-speed USB modules are included on select devices enabling simultaneous USB host and USB device to be active at the same time.  A single MCU can be used to communicate to multiple bus protocols for reduced design complexity and cost, making PIC32MK devices ideal for dual-USB applications such as digital audio or CAN-based implementations in the automotive and industrial markets. Development Support As with all PIC32 devices, the PIC32MK family is supported by Microchip’s MPLAB® Harmony Integrated Software Framework, MPLAB X Integrated Development Environment (IDE), MPLAB XC32 Compiler for PIC32, MPLAB ICD 3 In-Circuit Debugger and MPLAB REAL ICE™ In-Circuit Emulation system. Several additional tools are available including: The PIC32MK devices have peripheral block support for MathWorks® MATLAB® and Simulink® as well as open-source-based Scilab® for customers interested in numerical computation computing environments for engineering and scientific applications. Pricing and Availability Devices in the PIC32MK family are offered with up to 1 MB Flash and 256 KB SRAM in 64- and 100-pin TQFP and QFN packaging options. All devices are available today in volume production starting at $4.50 in 10K quantities.             For additional information, contact any Microchip sales representative or authorized worldwide distributor. To purchase products mentioned in this press release, go to Microchip’s easy-to-use online sales channel microchipDIRECT or contact one of Microchip’s authorized distribution partners. Resources High-res images available through Flickr or editorial contact (feel free to publish): About Microchip Technology Microchip Technology Inc. (NASDAQ:MCHP) is a leading provider of microcontroller, mixed-signal, analog and Flash-IP solutions, providing low-risk product development, lower total system cost and faster time to market for thousands of diverse customer applications worldwide.  Headquartered in Chandler, Arizona, Microchip offers outstanding technical support along with dependable delivery and quality.  For more information, visit the Microchip website at www.microchip.com. Note:  The Microchip name and logo, the Microchip logo, PIC and MPLAB are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. REAL ICE is a trademark of Microchip Technology Inc. in the U.S.A. and other countries.  All other trademarks mentioned herein are the property of their respective companies.


In a long-term effort to solve the high-resolution Mediator structure, we co-expressed Mediator subunits in Escherichia coli and determined crystal structures of nine subcomplexes12, 13. We eventually prepared cMed by co-expression of 15 Mediator subunits from S. cerevisiae5. Recombinant cMed was active in transcription and in stimulating CTD phosphorylation5. Cryo-electron microscopy (cryo-EM) revealed cMed regions that contact TFIIB and Pol II5. However, recombinant S. cerevisiae cMed failed to crystallize, impairing high-resolution structure determination. We have now solved the crystal structure of cMed (Methods). We prepared recombinant cMed from the fission yeast S. pombe, and improved protein solubility and yield by co-expression of Med1. To obtain crystals, we removed the flexible Med14 residues 581–879 and five C-terminal residues of Med11. Crystal dehydration improved the diffraction limit from ~8 to ~4 Å resolution. Complete diffraction data to 3.4 Å resolution were obtained with a collimated synchrotron beam. Phases were derived from a heavy-metal cluster derivative, incorporated selenomethionine, and the head module structure13. Interpretation of the electron density was facilitated by sequence markers and led to a refined structure with excellent stereochemistry (Fig. 1, Extended Data Fig. 1 and Extended Data Tables 1 and 2). The cMed structure comprises 15 subunits, and only lacks Med1, which probably dissociated during crystallization. The structure reveals the head and middle modules, and shows how the two modules interact (Fig. 1). The structure of the head module is unchanged compared with the free module13. The middle module structure confirms the topology derived previously by crosslinking and other methods10, 21, 22, and reveals details of the intricate and distinct folds of its eight subunits (Extended Data Fig. 2). The middle module is divided into five submodules5: the beam, plank, hook, and knob, and a newly defined ‘connector’ (Fig. 2). The beam buttresses the head module and consists mainly of the central region of Med14. This region contains two RWD-like23 and two UBC-like folds24. Med14 extends with its amino (N)- and C-terminal regions into the hook and tail module, respectively, consistent with its role as a ‘backbone’ of Mediator4, 5. The plank includes Med4 and Med9, which form a four-helix bundle domain as predicted25. The hook contains two such bundle domains25, one at its exposed end, formed by Med10 and the Med14 N-terminal region (Med14N), and one in the Med7C-Med21 dimer19, which is slightly opened to bind the Med10 C-terminal region21. Med19 meanders around the hook. The hook is flexibly linked to the connector by a conserved hinge in the Med7C/Med21 subcomplex19 that is required for Mediator–Pol II interaction26. The knob is a highly conserved, central element of cMed implicated in binding the CTD. It contains the Med7N–Med31 subcomplex27, four short helices in the C-terminal region of Med4 (Med4C), and three short helices in Med14. Compared with our structure, the knob is rotated by 180° in a recent model20 (Extended Data Fig. 3), questioning a proposal for how Mediator interacts with the CTD20. In addition, superposition of a previous head module–CTD peptide complex15 onto our cMed structure results in clashes of the modelled CTD peptide with Med4 (Extended Data Fig. 4). Thus the reported CTD positions15, 20 or the cMed structure, or both, will change upon Mediator binding to the CTD. The head and middle modules form a largely conserved interface that comprises four contact regions (interfaces I–IV) and two protein tethers (Extended Data Fig. 4). Interface I is formed between Med20 in the head module and Med14, and stabilizes the moveable jaw for binding Pol II and TFIIB5. Interface II is formed between Med17 in the fixed jaw of the head module and Med14. Interface III is formed between the knob and the head module spine and shoulder. Interface IV is formed between the Med6 shoulder and the hook, and is lost when the hook moves away from the head module by changes in the hinge. The head module subunits Med6 and Med17 contain flexibly linked13 terminal regions that form part of the beam and thus tether the middle module. The C-terminal helix α6 in Med6 (‘Med6C tether’) and the two helices that form the N-terminal region in Med17 (‘Med17N tether’) both associate with the Med14 beam in the middle module. The cMed structure enabled us to locate known mutations in the middle module, and in parts of head module subunits that were previously not visualized5, 13 (Fig. 3 and Extended Data Table 3). We first used the cMed structure to build a conservative and reliable homology model for the S. cerevisiae cMed (Methods, Supplementary Fig. 1 and Supplementary Data 1). The mutated sites were then located in the model and examined for their environment. This predicted that mutations often weaken interactions between the head and middle modules (Extended Data Fig. 4). In the med6-ts6 yeast strain, mutations in two residues in Med6C (M273, I275) are predicted to destabilize the Med6C tether. In the classical yeast mutation srb4-138 (ref. 17), the mutated residues L124 and E460 are located in the Med17N tether and interface II, respectively. Weakening of the head–middle interface in the srb4-138 strain explains why the head module dissociates from Mediator at elevated temperature28, leading to global changes in RNA synthesis activity5. Mutations that are predicted to impair middle module stability also lead to a general decrease in RNA synthesis (Extended Data Fig. 4d), showing that the middle module is globally required for transcription. The cMed structure also enabled us to obtain an atomic model of the cPIC–cMed complex (Extended Data Fig. 5). The S. cerevisiae cMed model was first placed into the cryo-EM reconstruction of a minimal cPIC–cMed complex5. After minor manual movements of the flexible hook, the fit was excellent, consistent with a high conservation of the cMed structure. We then replaced the cPIC model5 by our 3.6 Å structure of the cPIC18. The resulting atomic model of the cPIC–cMed complex comprises 35 polypeptides and includes Pol II, TBP, TFIIA, TFIIB, TFIIE, TFIIF, and cMed. The model confirms the known interfaces5 between cPIC and cMed, and shows that interface C5 is formed between the Pol II foot and the Med4–Med9 bundle in the plank. Finally, we fitted the obtained cPIC–cMed model into the recently reported low-resolution cryo-EM reconstruction of a PIC–Mediator complex20 (Fig. 4 and Supplementary Data 2). This confirmed the proposed location of the tail module5, 7, 11 that had been predicted on the basis of superposition of free Mediator reconstructions8, 9. It also showed that the exposed end of the hook, and the Med6 shoulder, reached near a density that was assigned to the TFIIH kinase subcomplex20. The hook also approached the TFIIH subunit Rad3 (ref. 29) (human XPD30) located in PIC reconstructions (Extended Data Fig. 5e). The observed contacts between Mediator and TFIIH are probably relevant for Mediator-stimulated CTD phosphorylation by TFIIH. The CTD apparently extends from the body of Pol II along the Mediator head–middle interface into a previously described cradle5. Residue K1725 at the end of the CTD crosslinks to three Med19 residues5, 20 that are located inside the cradle (Fig. 4). The CTD may be accommodated by changes in the head–middle module interface that is highly mobile (Extended Data Fig. 5b). It remains to be explored how exactly the CTD interacts with Mediator and how this results in presentation of the CTD to the TFIIH kinase located on the rim of the cradle. After our revised manuscript had been submitted, cryo-EM reconstructions were reported for the S. pombe Mediator in free form and bound to Pol II31. The EM-derived Mediator model31 differs from our crystal structure in regions of the middle module that were newly built31. In this model31, the hook and knob comprise regions that were assigned to different subunits, the beam contains regions with shifted amino-acid register, and the plank lacks sequence assignment (Extended Data Fig. 6). However, the position of S. pombe Mediator on Pol II31 is consistent with our previously reported location of S. cerevisiae Mediator on Pol II5 and with the PIC–cMed model presented here.


CHANDLER, Ariz., May 10, 2017 (GLOBE NEWSWIRE) -- The newest family of PIC32 microcontrollers (MCUs) is now available from Microchip Technology Inc. (NASDAQ:MCHP). The PIC32MK family features four highly integrated MCUs for precision dual Motor Control applications (PIC32MK MC) and eight MCUs packed with serial communication modules for General Purpose applications (PIC32MK GP). All MC and GP devices feature a 120 MHz 32-bit core that supports Digital Signal Processor (DSP) instructions. Additionally, to ease control algorithm development, a double-precision floating point unit is integrated into the MCU core enabling customers to utilize floating-point based modeling and simulation tools for code development. For more information about Microchip’s PIC32MK family visit: www.microchip.com/pic32mk. To increase efficiency and decrease the number of discrete devices needed in motor control applications, the high-performance PIC32MK MC devices combine 32-bit processing with advanced analog peripherals such as a quad 10 MHz op amp, high-speed comparators and motor-control optimized Pulse Width Modulation (PWM) modules. The devices also have Analog-to-Digital Converter (ADC) modules capable of total throughput of 25.45 Mega-Samples Per Second (MSPS) in 12-bit mode or 33.79 MSPS in 8-bit mode, enabling higher precision in motor control applications. The devices come with up to 1 MB Live Update Flash, 4 KB of EEPROM and 256 KB SRAM. “The PIC32MK family represents a continuation in the Microchip motor control lineup enabling traditional 8- and 16-bit customers to move to a 32-bit MCU for motor control while maintaining support through classic Microchip development tools,” said Rod Drake, vice president of Microchip’s MCU32 business unit. “The family also has general purpose MCUs with an extensive array of serial communications modules ideally suited for the industrial space.” With class-leading connectivity integration, the PIC32MK devices have up to four independent CAN 2.0 ports as well as six Universal Asynchronous Receiver/Transmitter (UART) modules, Local Interconnect Network (LIN) 1.2 and six Serial Peripheral Interface (SPI) or Inter-IC Sound (I2S) modules. Additionally, two complete full-speed USB modules are included on select devices enabling simultaneous USB host and USB device to be active at the same time.  A single MCU can be used to communicate to multiple bus protocols for reduced design complexity and cost, making PIC32MK devices ideal for dual-USB applications such as digital audio or CAN-based implementations in the automotive and industrial markets. Development Support As with all PIC32 devices, the PIC32MK family is supported by Microchip’s MPLAB® Harmony Integrated Software Framework, MPLAB X Integrated Development Environment (IDE), MPLAB XC32 Compiler for PIC32, MPLAB ICD 3 In-Circuit Debugger and MPLAB REAL ICE™ In-Circuit Emulation system. Several additional tools are available including: The PIC32MK devices have peripheral block support for MathWorks® MATLAB® and Simulink® as well as open-source-based Scilab® for customers interested in numerical computation computing environments for engineering and scientific applications. Pricing and Availability Devices in the PIC32MK family are offered with up to 1 MB Flash and 256 KB SRAM in 64- and 100-pin TQFP and QFN packaging options. All devices are available today in volume production starting at $4.50 in 10K quantities.             For additional information, contact any Microchip sales representative or authorized worldwide distributor. To purchase products mentioned in this press release, go to Microchip’s easy-to-use online sales channel microchipDIRECT or contact one of Microchip’s authorized distribution partners. Resources High-res images available through Flickr or editorial contact (feel free to publish): About Microchip Technology Microchip Technology Inc. (NASDAQ:MCHP) is a leading provider of microcontroller, mixed-signal, analog and Flash-IP solutions, providing low-risk product development, lower total system cost and faster time to market for thousands of diverse customer applications worldwide.  Headquartered in Chandler, Arizona, Microchip offers outstanding technical support along with dependable delivery and quality.  For more information, visit the Microchip website at www.microchip.com. Note:  The Microchip name and logo, the Microchip logo, PIC and MPLAB are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. REAL ICE is a trademark of Microchip Technology Inc. in the U.S.A. and other countries.  All other trademarks mentioned herein are the property of their respective companies.


CHANDLER, Ariz., May 09, 2017 (GLOBE NEWSWIRE) -- A new Digitally Enhanced Power Analog (DEPA) buck controller for DC-DC power conversion is now available from Microchip Technology Inc. (NASDAQ:MCHP). This device offers more flexibility than any other analog control architecture on the market today. The single-chip solution controls DC-DC converters and is capable of accepting a high-voltage input (up to 42V) while simultaneously regulating a wide output voltage range (0.3V to 16V without any external components or drivers). For more information, visit: www.microchip.com/MCP19123. The internal PIC® microcontroller in the MCP19122/3 can dynamically adjust the operating frequency, over- and under-voltage lockout thresholds, current limits, soft-start, voltage or current output setpoints and maximum duty cycle. This level of configurability offers many application benefits. For example, the MCP19123 can dynamically adjust the voltage output to meet USB Power Delivery requirements, while also adjusting the output over-voltage lockout to maintain tight protection limits corresponding to each output voltage level. The MCP19123 buck controller offers many unique capabilities, including a programmable differential input amplifier used to optimize performance and minimize system voltage error. This configurability allows for a wide output voltage range commonly seen in USB power and battery charger applications. Improving integration in larger systems, the device can synchronize to an external clock and voltage reference, or provide the internal system clock and reference to other devices for synchronization. In server or communications equipment, this allows for seamless power up and accurate tracking of power consumption throughout the board. For high-power applications, multiple outputs can operate in parallel providing system redundancy for improved system reliability. Combined with an on-board programmable diagnostic and fault detection capability that is unmatched in the industry, the MCP19122/3 is ideal for high-performance intelligent power applications. This device also offers excellent accuracy for an adjustable output power supply. A MCP19122/3 DC-DC converter implementation can maintain an initial 0.5 percent or better output voltage accuracy. In addition to the tight voltage regulation, the MCP19122/3 is designed to deliver industry-leading current measurement by using a lossless inductor current sense method with specialized internal measurement calibrations. The device can directly accept a common mode signal up to 16V and report the load current to within 5 percent accuracy for most applications, with an emulated average current mode control for hardware-based cycle-by-cycle current limiting. “Microchip is one of the few companies that truly understands both analog power control and digital controllers,” said Rich Simoncic, vice president of Microchip’s Analog, Power and Interface Division. “The novel combination of digital management and analog power control methods in our DEPA portfolio allows for many application benefits that no other company can offer.” Development Support The devices are supported by Microchip’s suite of programming and development tools including MPLAB® X Integrated Development Environment (IDE) and the MPLAB XC8 complier. Pricing and Availability The MCP19122 is available today in a 4 x 4 QFN package for sampling and in volume production starting at $2.94 each in 10,000 unit quantities. The MCP19123 is available today in a 5 x 5 QFN package starting at $3.17 each in 10,000 unit quantities. For additional information, contact any Microchip sales representative or authorized worldwide distributor, or visit Microchip’s website. To purchase products mentioned in this press release, go Microchip’s easy-to-use online sales channel microchipDIRECT or contact one of Microchip’s authorized distribution partners. Resources High-res images available through Flickr or editorial contact (feel free to publish): About Microchip Technology Microchip Technology Inc. (NASDAQ:MCHP) is a leading provider of microcontroller, mixed-signal, analog and Flash-IP solutions, providing low-risk product development, lower total system cost and faster time to market for thousands of diverse customer applications worldwide. Headquartered in Chandler, Arizona, Microchip offers outstanding technical support along with dependable delivery and quality. For more information, visit the Microchip website at www.microchip.com. Note: The Microchip name and logo, the Microchip logo, PIC and MPLAB are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. All other trademarks mentioned herein are the property of their respective companies.


CHANDLER, Ariz., May 09, 2017 (GLOBE NEWSWIRE) -- A new Digitally Enhanced Power Analog (DEPA) buck controller for DC-DC power conversion is now available from Microchip Technology Inc. (NASDAQ:MCHP). This device offers more flexibility than any other analog control architecture on the market today. The single-chip solution controls DC-DC converters and is capable of accepting a high-voltage input (up to 42V) while simultaneously regulating a wide output voltage range (0.3V to 16V without any external components or drivers). For more information, visit: www.microchip.com/MCP19123. The internal PIC® microcontroller in the MCP19122/3 can dynamically adjust the operating frequency, over- and under-voltage lockout thresholds, current limits, soft-start, voltage or current output setpoints and maximum duty cycle. This level of configurability offers many application benefits. For example, the MCP19123 can dynamically adjust the voltage output to meet USB Power Delivery requirements, while also adjusting the output over-voltage lockout to maintain tight protection limits corresponding to each output voltage level. The MCP19123 buck controller offers many unique capabilities, including a programmable differential input amplifier used to optimize performance and minimize system voltage error. This configurability allows for a wide output voltage range commonly seen in USB power and battery charger applications. Improving integration in larger systems, the device can synchronize to an external clock and voltage reference, or provide the internal system clock and reference to other devices for synchronization. In server or communications equipment, this allows for seamless power up and accurate tracking of power consumption throughout the board. For high-power applications, multiple outputs can operate in parallel providing system redundancy for improved system reliability. Combined with an on-board programmable diagnostic and fault detection capability that is unmatched in the industry, the MCP19122/3 is ideal for high-performance intelligent power applications. This device also offers excellent accuracy for an adjustable output power supply. A MCP19122/3 DC-DC converter implementation can maintain an initial 0.5 percent or better output voltage accuracy. In addition to the tight voltage regulation, the MCP19122/3 is designed to deliver industry-leading current measurement by using a lossless inductor current sense method with specialized internal measurement calibrations. The device can directly accept a common mode signal up to 16V and report the load current to within 5 percent accuracy for most applications, with an emulated average current mode control for hardware-based cycle-by-cycle current limiting. “Microchip is one of the few companies that truly understands both analog power control and digital controllers,” said Rich Simoncic, vice president of Microchip’s Analog, Power and Interface Division. “The novel combination of digital management and analog power control methods in our DEPA portfolio allows for many application benefits that no other company can offer.” Development Support The devices are supported by Microchip’s suite of programming and development tools including MPLAB® X Integrated Development Environment (IDE) and the MPLAB XC8 complier. Pricing and Availability The MCP19122 is available today in a 4 x 4 QFN package for sampling and in volume production starting at $2.94 each in 10,000 unit quantities. The MCP19123 is available today in a 5 x 5 QFN package starting at $3.17 each in 10,000 unit quantities. For additional information, contact any Microchip sales representative or authorized worldwide distributor, or visit Microchip’s website. To purchase products mentioned in this press release, go Microchip’s easy-to-use online sales channel microchipDIRECT or contact one of Microchip’s authorized distribution partners. Resources High-res images available through Flickr or editorial contact (feel free to publish): About Microchip Technology Microchip Technology Inc. (NASDAQ:MCHP) is a leading provider of microcontroller, mixed-signal, analog and Flash-IP solutions, providing low-risk product development, lower total system cost and faster time to market for thousands of diverse customer applications worldwide. Headquartered in Chandler, Arizona, Microchip offers outstanding technical support along with dependable delivery and quality. For more information, visit the Microchip website at www.microchip.com. Note: The Microchip name and logo, the Microchip logo, PIC and MPLAB are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. All other trademarks mentioned herein are the property of their respective companies.


News Article | May 9, 2017
Site: globenewswire.com

MAYNARD, Mass., May 09, 2017 (GLOBE NEWSWIRE) -- Acacia Communications, Inc. (NASDAQ:ACIA), a leading provider of high-speed coherent optical interconnect products, today reported financial results for its first quarter ended March 31, 2017. “We are pleased that our first quarter results came in stronger than we expected at the start of the quarter driven by demand for our CFP and flex-400G products around the world,” said Raj Shanmugaraj, President and Chief Executive Officer of Acacia Communications.  “During the quarter, we made good progress on ramping production of our CFP2-ACO and CFP2-DCO modules with our contract manufacturers and we continue to see strong customer interest for these products.  We believe that our continued innovation with products like our CFP2-DCO will further advance our technology leadership position and contribute to our growth in the second half of 2017 and beyond.” “We believe that our strong balance sheet, which shows a significant cash position and no debt, provides us with the financial flexibility to continue to invest in product development to further strengthen our competitive position and enable us to bring products to those markets that require a rapid pace of innovation, like the DCI market,” said John Gavin, Chief Financial Officer of Acacia Communications.  “For example, we recently announced our next generation Pico DSP ASIC which, when combined with our ball grid array PIC, will support transmission speeds of up to 1.2 Tbps with two carriers of 600 Gbps each.  Pico will power our AC1200 module and is focused on DCI applications.” Results for the First Quarter of 2017 Outlook for the Second Quarter of 2017 The following statements are based on current expectations. These statements are forward-looking and actual results may differ materially, as a result of, among other things, the important factors discussed at the end of this press release. Acacia Communications disclaims any obligation to update these forward-looking statements. Acacia Communications’ guidance for its second quarter ending June 30, 2017 is: *Non-GAAP gross margin, non-GAAP income from operations, non-GAAP net income, EBITDA, adjusted EBITDA and non-GAAP diluted EPS are non-GAAP financial measures that are not prepared in accordance with generally accepted accounting principles (GAAP).  Please refer below to Use of Non-GAAP Financial Information for descriptions of these non-GAAP financial measures and to the Reconciliation of GAAP Measures to Non-GAAP Measures, attached as Schedule D, for reconciliations of these and other of our non-GAAP financial measures to the closest GAAP measures. Acacia Communications has not reconciled the above guidance as to non-GAAP net income or non-GAAP diluted EPS to GAAP net income or GAAP EPS because the expected tax benefits derived from any employee equity awards during the second quarter of 2017 cannot be reasonably calculated or predicted at this time. Accordingly, a reconciliation is not available without unreasonable effort. Acacia Communications will host a conference call to discuss its results for the first quarter of 2017, recent developments and the Company’s business outlook and strategy at 5 p.m. Eastern Time today. The live webcast of the call, along with the Company's earnings press release, can be accessed at the Acacia Communications’ Investor Relations website at http://ir.acacia-inc.com. The U.S. dial-in for the call is 1-877-407-8293 (1-201-689-8349 for non-U.S. callers). Please ask to be joined to the Acacia Communications call. A replay of the conference call will be available until May 23, 2017, at 11:59 p.m. Eastern Time, while an archived version of the webcast will be available on the Acacia Communications’ Investor Relations website for 90 days. The U.S. dial-in for the conference call replay is 1-877-660-6853 (1-201-612-7415 for non-U.S. callers). The replay access code is 13660313. Use of Non-GAAP Financial Information This press release includes non-GAAP financial measures that are not prepared in accordance with, nor an alternative to, generally accepted accounting principles (GAAP). In addition, these non-GAAP financial measures are not based on any standardized methodology prescribed by GAAP and are not necessarily comparable to similarly-titled measures presented by other companies. Schedule D of this press release provides reconciliations of Acacia Communications’ non-GAAP gross profit, non-GAAP gross margin, non-GAAP research and development expenses, non-GAAP sales, general and administrative expenses, non-GAAP operating expenses, non-GAAP income from operations, non-GAAP net income, non-GAAP effective tax rate, non-GAAP diluted EPS, EBITDA and adjusted EBITDA to their most comparable GAAP financial measure. Acacia Communications believes that providing these non-GAAP financial measures to investors, in addition to providing the corresponding GAAP measures, provides investors the benefit of viewing the Company’s performance using the same financial metrics that its management team uses in making many key decisions and evaluating how its results of operations may look in the future. Acacia Communications’ management does not believe that items not involving cash expenditures, such as non-cash compensation related to equity awards and redeemable convertible preferred stock warrant liability changes derived from mark-to-market adjustments, are part of its critical decision making process. Therefore, Acacia Communications excludes those items, as applicable, from non-GAAP gross profit, non-GAAP gross margin, non-GAAP research and development expenses, non-GAAP sales, general and administrative expenses, non-GAAP operating expenses, non-GAAP income from operations, non-GAAP net income, non-GAAP effective tax rate, non-GAAP diluted EPS, EBITDA and adjusted EBITDA. Acacia Communications’ non-GAAP financial measures reflect adjustments based on the metrics described below, as well as the related income tax effects. The income tax effect of these non-GAAP adjustments is determined by recalculating income tax expense excluding these adjustments. Non-GAAP gross profit and gross margin.    Acacia Communications defines non-GAAP gross profit as gross profit as reported on its consolidated income statements, excluding the impact of stock-based compensation, which is a non-cash charge. Acacia Communications defines non-GAAP gross margin as the non-GAAP gross profit divided by revenue as reported on its consolidated income statements.  Acacia Communications has presented non-GAAP gross profit and gross margin because the Company believes that the exclusion of stock-based compensation facilitates comparisons of its results of operations to other companies in its industry.                                                                        Non-GAAP research and development expenses.    Acacia Communications defines non-GAAP research and development expenses as research and development expenses as reported on the Company’s consolidated income statements, excluding the impact of stock-based compensation. Acacia Communications has presented non-GAAP research and development expenses because the Company believes that the exclusion of stock-based compensation facilitates comparisons of its results of operations to other companies in its industry. Non-GAAP sales, general and administrative expenses.    Acacia Communications defines non-GAAP sales, general and administrative expenses as sales, general and administrative expenses as reported on the Company’s consolidated income statements, excluding the impact of stock-based compensation. Acacia Communications has presented non-GAAP sales, general and administrative expenses because the Company believes that the exclusion of stock-based compensation facilitates comparisons of its results of operations to other companies in its industry. Non-GAAP operating expenses.    Acacia Communications defines non-GAAP operating expenses as operating expenses as reported on the Company’s consolidated income statements, excluding the impact of stock-based compensation. Acacia Communications has presented non-GAAP operating expenses because the Company believes that the exclusion of stock-based compensation facilitates comparisons of its results of operations to other companies in its industry. Non-GAAP income from operations.    Acacia Communications defines non-GAAP income from operations as income from operations as reported on the Company’s consolidated income statements, excluding the impact of stock-based compensation. Acacia Communications has presented non-GAAP income from operations because the Company believes that the exclusion of stock-based compensation facilitates comparisons of its results of operations to other companies in its industry. Non-GAAP net income, non-GAAP effective tax rate and non-GAAP diluted EPS.    Acacia Communications defines non-GAAP net income as net income as reported on the Company’s consolidated income statements, excluding the impact of stock-based compensation and the change in fair value of the Company’s preferred stock warrant liability, both of which are non-cash charges, and the tax effects of those excluded items and the release and reversal of a valuation allowance against deferred tax assets. Acacia Communications defines non-GAAP effective tax rate as the non-GAAP provision for income taxes divided by non-GAAP income before provision for income taxes.  Non-GAAP provision for income taxes is defined as the (benefit) provision for income taxes as reported on the Company’s consolidated income statements, as adjusted for the tax effects of excluding stock-based compensation expense and the Company’s preferred stock warrant liability.  Non-GAAP income before provision for income taxes is defined as GAAP income before (benefit) provision for income taxes, excluding stock-based compensation expense and the Company’s preferred stock warrant liability. In order to calculate non-GAAP diluted EPS, Acacia Communications uses a non-GAAP weighted-average share count. The Company defines non-GAAP weighted-average shares used to compute non-GAAP diluted EPS as GAAP weighted-average shares used to compute diluted EPS, adjusted to reflect the conversion of its redeemable convertible preferred stock into common stock and the conversion of its redeemable convertible preferred stock warrants into common stock warrants, both as if they had occurred at the beginning of the period. Acacia Communications has presented non-GAAP net income, non-GAAP effective tax rate and non-GAAP diluted EPS because the Company believes that the exclusion of the items discussed above facilitates comparisons of its results of operations to other companies in its industry. EBITDA and Adjusted EBITDA.    Acacia Communications defines EBITDA as net income as reported on the Company’s consolidated income statements before depreciation, interest (income) expense, net, and its (benefit) provision for income taxes. Acacia Communications defines adjusted EBITDA as EBITDA excluding the impact of stock-based compensation and the change in fair value of the Company’s preferred stock warrant liability. Acacia Communications has presented adjusted EBITDA because it is a key measure used by its management and board of directors to understand and evaluate the Company’s operating performance, to establish budgets and to develop operational goals for managing its business. In particular, Acacia Communications believes that the exclusion of the amounts eliminated in calculating adjusted EBITDA can provide a useful measure for period-to-period comparisons of its core operating performance. Acacia Communications uses these non-GAAP financial measures to evaluate its operating performance and trends, and make planning decisions. Acacia Communications believes that each of these non-GAAP financial measures helps identify underlying trends in its business that could otherwise be masked by the effect of the items that the Company excludes. Accordingly, Acacia Communications believes that these financial measures provide useful information to investors and others in understanding and evaluating its operating results, enhancing the overall understanding of the Company’s past performance and future prospects, and allowing for greater transparency with respect to key financial metrics used by its management in its financial and operational decision-making. Acacia Communications’ non-GAAP financial measures are not prepared in accordance with GAAP, and should not be considered in isolation of, or as an alternative to, measures prepared in accordance with GAAP. There are a number of limitations related to the use of these non-GAAP financial measures rather than gross profit, gross margin, research and development expenses, sales, general and administrative expenses, operating expenses, income from operations, net income, effective tax rate or diluted EPS, which are the nearest GAAP equivalents. Some of these limitations are: Because of these limitations, non-GAAP financial measures should be considered along with other operating and financial performance measures presented in accordance with GAAP. Acacia Communications’ use of non-GAAP financial measures, and the underlying methodology when excluding certain items, is not necessarily an indication of the results of operations that may be expected in the future, or that Acacia Communications will not, in fact, record such items in future periods. Investors should consider Acacia Communications’ non-GAAP financial measures in conjunction with the corresponding GAAP financial measures. Acacia Communications develops, manufactures and sells high-speed coherent optical interconnect products that are designed to transform communications networks through improvements in performance, capacity and cost. By leveraging silicon technology to build optical interconnects, a process Acacia Communications refers to as the “siliconization of optical interconnect,” Acacia Communications is able to offer products at higher speeds and density with lower power consumption, that meet the needs of cloud and service providers and can be easily integrated in a cost-effective manner with existing network equipment. www.acacia-inc.com. This press release includes statements concerning Acacia Communications and its future expectations, plans and prospects that constitute "forward-looking statements" within the meaning of the Private Securities Litigation Reform Act of 1995. For this purpose, any statements contained herein that are not statements of historical fact may be deemed to be forward-looking statements. Without limiting the foregoing, the words “may,” “should,” “expects,” “plans,” “anticipates,” “could,” “intends,” “target,” “projects,” “contemplates,” “believes,” “estimates,” “predicts,” “potential” or “continue” or the negative of these terms or other similar expressions are intended to identify forward-looking statements. Acacia Communications has based these forward-looking statements largely on its current expectations and projections about future events and financial trends that the Company believes may affect its business, financial condition and results of operations. These forward-looking statements speak only as of the date of this press release and are subject to a number of risks, uncertainties and assumptions including, without limitation, the Company’s anticipated growth strategies, its expectations regarding competition, the anticipated trends and challenges in its business and the market in which Acacia Communications operates, including those that may affect its customers and their demand for Acacia Communications’ products, its expectations regarding, and the stability of, its supply chain and manufacturing, the scope, progress, expansion and costs of developing and commercializing its products, the size and growth of the potential markets for its products and the ability to serve those markets, regulatory developments in the United States and foreign countries, including under export control laws or regulations that could impede its ability to sell its products to customers in certain foreign jurisdictions, and other risks set forth under the caption "Risk Factors" in the Company's public reports filed with the SEC, including the Company's Annual Report on Form 10-K for the year ended December 31, 2016 filed with the SEC and its Quarterly Report on Form 10-Q for the fiscal quarter ended March 31, 2017 to be filed with the SEC. Acacia Communications assumes no obligation to update any forward-looking statements contained in this press release as a result of new information, future events or otherwise.


CHANDLER, Ariz., May 09, 2017 (GLOBE NEWSWIRE) -- A new Digitally Enhanced Power Analog (DEPA) buck controller for DC-DC power conversion is now available from Microchip Technology Inc. (NASDAQ:MCHP). This device offers more flexibility than any other analog control architecture on the market today. The single-chip solution controls DC-DC converters and is capable of accepting a high-voltage input (up to 42V) while simultaneously regulating a wide output voltage range (0.3V to 16V without any external components or drivers). For more information, visit: www.microchip.com/MCP19123. The internal PIC® microcontroller in the MCP19122/3 can dynamically adjust the operating frequency, over- and under-voltage lockout thresholds, current limits, soft-start, voltage or current output setpoints and maximum duty cycle. This level of configurability offers many application benefits. For example, the MCP19123 can dynamically adjust the voltage output to meet USB Power Delivery requirements, while also adjusting the output over-voltage lockout to maintain tight protection limits corresponding to each output voltage level. The MCP19123 buck controller offers many unique capabilities, including a programmable differential input amplifier used to optimize performance and minimize system voltage error. This configurability allows for a wide output voltage range commonly seen in USB power and battery charger applications. Improving integration in larger systems, the device can synchronize to an external clock and voltage reference, or provide the internal system clock and reference to other devices for synchronization. In server or communications equipment, this allows for seamless power up and accurate tracking of power consumption throughout the board. For high-power applications, multiple outputs can operate in parallel providing system redundancy for improved system reliability. Combined with an on-board programmable diagnostic and fault detection capability that is unmatched in the industry, the MCP19122/3 is ideal for high-performance intelligent power applications. This device also offers excellent accuracy for an adjustable output power supply. A MCP19122/3 DC-DC converter implementation can maintain an initial 0.5 percent or better output voltage accuracy. In addition to the tight voltage regulation, the MCP19122/3 is designed to deliver industry-leading current measurement by using a lossless inductor current sense method with specialized internal measurement calibrations. The device can directly accept a common mode signal up to 16V and report the load current to within 5 percent accuracy for most applications, with an emulated average current mode control for hardware-based cycle-by-cycle current limiting. “Microchip is one of the few companies that truly understands both analog power control and digital controllers,” said Rich Simoncic, vice president of Microchip’s Analog, Power and Interface Division. “The novel combination of digital management and analog power control methods in our DEPA portfolio allows for many application benefits that no other company can offer.” Development Support The devices are supported by Microchip’s suite of programming and development tools including MPLAB® X Integrated Development Environment (IDE) and the MPLAB XC8 complier. Pricing and Availability The MCP19122 is available today in a 4 x 4 QFN package for sampling and in volume production starting at $2.94 each in 10,000 unit quantities. The MCP19123 is available today in a 5 x 5 QFN package starting at $3.17 each in 10,000 unit quantities. For additional information, contact any Microchip sales representative or authorized worldwide distributor, or visit Microchip’s website. To purchase products mentioned in this press release, go Microchip’s easy-to-use online sales channel microchipDIRECT or contact one of Microchip’s authorized distribution partners. Resources High-res images available through Flickr or editorial contact (feel free to publish): About Microchip Technology Microchip Technology Inc. (NASDAQ:MCHP) is a leading provider of microcontroller, mixed-signal, analog and Flash-IP solutions, providing low-risk product development, lower total system cost and faster time to market for thousands of diverse customer applications worldwide. Headquartered in Chandler, Arizona, Microchip offers outstanding technical support along with dependable delivery and quality. For more information, visit the Microchip website at www.microchip.com. Note: The Microchip name and logo, the Microchip logo, PIC and MPLAB are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. All other trademarks mentioned herein are the property of their respective companies.


News Article | May 9, 2017
Site: globenewswire.com

SUNNYVALE, Calif., May 09, 2017 (GLOBE NEWSWIRE) -- Infinera, a provider of Intelligent Transport Networks, announced a successful subsea field test with Canalink across its subsea cable. The test, conducted with the Infinera Infinite Capacity Engine (ICE4) and featuring Infinera's fourth-generation photonic integrated circuit (PIC), demonstrated the capability to upgrade the cable capacity 13-fold. Canalink, a wholly-owned subsidiary of the ITER group, owns a system of undersea fiber optic cables that link the Canary Islands with the Iberian Peninsula and the western coast of Africa. Canalink also has exchange agreements with other operators, and participates in undersea cable consortia aiming to connect Europe with Africa, transforming Tenerife, and the D-Alix datacenter specifically, into a node for the massive exchange of neutral data traffic. The test was conducted on Canalink’s 1,393 kilometer subsea cable, linking the Conil landing point on the Spanish mainland with Tenerife in the Canary Islands. Conducted across three fully-loaded channel plans at 37.5 gigahertz (GHz), 50 GHz and 25 GHz channel spacing, the test validated advanced compensation techniques and new modulation schemes including: “The successful field test with Infinera demonstrated that we can achieve approximately 13 times more capacity than we initially estimated on our subsea link,” said Carlos Suárez, General Director of Canalink. “Infinera's Infinite Capacity Engine and its innovative technology designed for subsea operators prove that its deployment can enable us to protect our investment and maximize the use of our infrastructure.” “Infinera is committed to bringing advanced capabilities to the subsea market, and we are pleased to enable Canalink to maximize capacity on their systems,” said Scott Jackson, Infinera Vice President, Subsea Business Group. “This test validates the benefits of ICE4 Nyquist subcarriers and SD-FEC gain sharing, enabling subsea cables to move to higher modulation formats for increased fiber capacity and greater return on the asset.” Infinera introduced the Infinite Capacity Engine-based subsea platforms, including the XTS‑3300 and XTS‑3600 meshponders, and upgraded its DTN-X XTC Series to 12 terabits per second (Tb/s) earlier this year. The new platforms feature Infinera’s Advanced Coherent Toolkit (ACT), which delivers innovations including Nyquist subcarriers, SD-FEC gain sharing, and matrix-enhanced phase-shift keying (ME-PSK). About Infinera Infinera (NASDAQ:INFN) provides Intelligent Transport Networks, enabling carriers, cloud operators, governments and enterprises to scale network bandwidth, accelerate service innovation and automate optical network operations. Infinera’s end-to-end packet-optical portfolio is designed for long-haul, subsea, data center interconnect and metro applications. Infinera’s unique large scale photonic integrated circuits enable innovative optical networking solutions for the most demanding networks. To learn more about Infinera visit www.infinera.com, follow us on Twitter @Infinera and read our latest blog posts at www.infinera.com/blog. Infinera and the Infinera logo are registered trademarks of Infinera Corporation. This press release contains forward-looking statements including, but not limited to the potential operational, technical and economic benefits of deploying Infinera products and solutions on subsea networks. These statements are not guarantees of results and should not be considered as an indication of future activity or future performance. Actual results may vary materially from these expectations as a result of various risks and uncertainties. Information about these risks and uncertainties, and other risks and uncertainties that affect Infinera’s business, is contained in the risk factors section and other sections of Infinera’s Annual Report on Form 10-K for the year ended December 31, 2016 as filed with the SEC on February 23, 2017, as well subsequent reports filed with or furnished to the SEC. These reports are available on Infinera’s website at www.infinera.com and the SEC’s website at www.sec.gov. Infinera assumes no obligation to, and does not currently intend to, update any such forward-looking statements.


CHANDLER, Ariz., May 10, 2017 (GLOBE NEWSWIRE) -- The newest family of PIC32 microcontrollers (MCUs) is now available from Microchip Technology Inc. (NASDAQ:MCHP). The PIC32MK family features four highly integrated MCUs for precision dual Motor Control applications (PIC32MK MC) and eight MCUs packed with serial communication modules for General Purpose applications (PIC32MK GP). All MC and GP devices feature a 120 MHz 32-bit core that supports Digital Signal Processor (DSP) instructions. Additionally, to ease control algorithm development, a double-precision floating point unit is integrated into the MCU core enabling customers to utilize floating-point based modeling and simulation tools for code development. For more information about Microchip’s PIC32MK family visit: www.microchip.com/pic32mk. To increase efficiency and decrease the number of discrete devices needed in motor control applications, the high-performance PIC32MK MC devices combine 32-bit processing with advanced analog peripherals such as a quad 10 MHz op amp, high-speed comparators and motor-control optimized Pulse Width Modulation (PWM) modules. The devices also have Analog-to-Digital Converter (ADC) modules capable of total throughput of 25.45 Mega-Samples Per Second (MSPS) in 12-bit mode or 33.79 MSPS in 8-bit mode, enabling higher precision in motor control applications. The devices come with up to 1 MB Live Update Flash, 4 KB of EEPROM and 256 KB SRAM. “The PIC32MK family represents a continuation in the Microchip motor control lineup enabling traditional 8- and 16-bit customers to move to a 32-bit MCU for motor control while maintaining support through classic Microchip development tools,” said Rod Drake, vice president of Microchip’s MCU32 business unit. “The family also has general purpose MCUs with an extensive array of serial communications modules ideally suited for the industrial space.” With class-leading connectivity integration, the PIC32MK devices have up to four independent CAN 2.0 ports as well as six Universal Asynchronous Receiver/Transmitter (UART) modules, Local Interconnect Network (LIN) 1.2 and six Serial Peripheral Interface (SPI) or Inter-IC Sound (I2S) modules. Additionally, two complete full-speed USB modules are included on select devices enabling simultaneous USB host and USB device to be active at the same time.  A single MCU can be used to communicate to multiple bus protocols for reduced design complexity and cost, making PIC32MK devices ideal for dual-USB applications such as digital audio or CAN-based implementations in the automotive and industrial markets. Development Support As with all PIC32 devices, the PIC32MK family is supported by Microchip’s MPLAB® Harmony Integrated Software Framework, MPLAB X Integrated Development Environment (IDE), MPLAB XC32 Compiler for PIC32, MPLAB ICD 3 In-Circuit Debugger and MPLAB REAL ICE™ In-Circuit Emulation system. Several additional tools are available including: The PIC32MK devices have peripheral block support for MathWorks® MATLAB® and Simulink® as well as open-source-based Scilab® for customers interested in numerical computation computing environments for engineering and scientific applications. Pricing and Availability Devices in the PIC32MK family are offered with up to 1 MB Flash and 256 KB SRAM in 64- and 100-pin TQFP and QFN packaging options. All devices are available today in volume production starting at $4.50 in 10K quantities.             For additional information, contact any Microchip sales representative or authorized worldwide distributor. To purchase products mentioned in this press release, go to Microchip’s easy-to-use online sales channel microchipDIRECT or contact one of Microchip’s authorized distribution partners. Resources High-res images available through Flickr or editorial contact (feel free to publish): About Microchip Technology Microchip Technology Inc. (NASDAQ:MCHP) is a leading provider of microcontroller, mixed-signal, analog and Flash-IP solutions, providing low-risk product development, lower total system cost and faster time to market for thousands of diverse customer applications worldwide.  Headquartered in Chandler, Arizona, Microchip offers outstanding technical support along with dependable delivery and quality.  For more information, visit the Microchip website at www.microchip.com. Note:  The Microchip name and logo, the Microchip logo, PIC and MPLAB are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. REAL ICE is a trademark of Microchip Technology Inc. in the U.S.A. and other countries.  All other trademarks mentioned herein are the property of their respective companies.

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