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Hiremath D.,PES University | Rajeshwari B.,PESIT
IEEE Region 10 Annual International Conference, Proceedings/TENCON | Year: 2017

Implementation of the Pipelined Radix-2 FFT using Single path Delay Commutator and Single path Delay Feedback (SDC & SDF) architecture is presented. This architecture includes 3 stages of the SDC and 1 stage of SDF. This approach makes use of less hardware resources and also shares the same resources as it is pipelined architecture. Thus reducing the number of complex multipliers and the adders used in the architecture as compared with other Radix-2 SDC and SDF architecture when used alone. © 2016 IEEE.

Akhila N.S.,PESIT | Koppad D.,PESIT
2016 IEEE Annual India Conference, INDICON 2016 | Year: 2016

Arithmetic computations can be on integer or floating(real) numbers. In digital systems, ALU handles arithmetic operations. However, ALU is not suitable for handling operations on real numbers as the result may not be precise and accurate. Hence to perform operations on real numbers digital systems use a dedicated unit called floating point unit(FPU). In this paper, the designed FPU is single precision and operates on IEEE - 754 - 2008 format. The available arithmetic operations on this FPU are floating point multiplication, division, addition and subtraction. The designed FPU can operate on both normal(normalized) and subnormal(denormalized) numbers present in floating point numbers. In this paper, stuck-at fault model using Built in self test(BIST) method is designed for the floating point unit to check the fault in the design. Basic idea behind the BIST is testing the device by itself. The proposed design is modified for parallel testing by dividing the FPU into 3 independent blocks. In this method when one of the blocks is in its normal operation the other block of the FPU is tested in parallel. The design's RTL code is written in Verilog HDL and Xilinx Vivado 2015 is used for simulation. The proposed method reduces the dynamic power by 10.47% compared to the conventional method. © 2016 IEEE.

Sharma J.,PESIT | Koppad D.,PESIT
2016 IEEE Annual India Conference, INDICON 2016 | Year: 2016

Cryptography plays an important role in the security of data. Even though the data is encrypted it can be altered while transmitting on the network so data should be verified using a digital signature. Hashing algorithms are used to create these digital signatures for verification of the data received. Hashing algorithm like Secure hash algorithm-3 SHA-3(512) (keccak) is designed which has a fixed output length of 512-bits. Then to improve on power a low-power technique such as latch based clock gating technique is used. After applying these techniques all the designs are compared in terms of power, delay and frequency. SHA-3 algorithm is designed using Verilog HDL and simulated in Xilinx ISE v14.2. © 2016 IEEE.

Poornima T.,PESIT | Nayak J.,National Institute of Technology Karnataka
Journal of Applied Electrochemistry | Year: 2011

The corrosion inhibition of the aged 18 Ni 250 grade maraging steel in 0.5 M sulfuric acid by 3,4-dimethoxybenzaldehydethiosemicarbazone(DMBTSC) has been investigated by potentiodynamic polarization and electrochemical impedance spectroscopy(EIS) techniques. The inhibition efficiency increased with the increase in inhibitor concentration and decreased with the increase in temperature. Polarization curves indicated mixed type inhibition behavior affecting both cathodic and anodic corrosion currents. The thermodynamic parameters of corrosion and adsorption processes were evaluated. The adsorption of DMBTSC on the aged maraging steel surface was found to obey the Langmuir adsorption isotherm model, and the calculated Gibb's free energy values confirm the spontaneous adsorption. The results obtained by the two techniques were in good agreement. © 2010 Springer Science+Business Media B.V.

Poornima T.,PESIT | Nayak J.,National Institute of Technology Karnataka | Nityananda Shetty A.,National Institute of Technology Karnataka
Corrosion Science | Year: 2011

4-(N,N-diethylamino)benzaldehyde thiosemicarbazone (DEABT) was studied for its corrosion inhibition property on the corrosion of aged 18 Ni 250 grade maraging steel in 0.67M phosphoric acid at 30-50°C by potentiodynamic polarization, EIS and weight loss techniques. Inhibition efficiency of DEABT was found to increase with the increase in DEABT concentration and decrease with the increase in temperature. The activation energy Ea and other thermodynamic parameters (ΔGads 0, ΔHads 0, ΔSads 0) have been evaluated and discussed. The adsorption of DEABT on aged maraging steel surface obeys the Langmuir adsorption isotherm model and the inhibitor showed mixed type inhibition behavior. © 2011 Elsevier Ltd.

Poornima T.,PESIT | Jagannatha N.,National Institute of Technology Karnataka | Nityananda Shetty A.,National Institute of Technology Karnataka
Portugaliae Electrochimica Acta | Year: 2010

The corrosion behavior of aged and annealed sample of 18 Ni 250 grade maraging steel was investigated in varied conditions of concentration and temperature of sulphuric acid medium, using electrochemical techniques like Tafel polarization and electrochemical impedance spectroscopy (EIS). The results obtained from both the techniques are in good agreement. These results have shown increase in corrosion rate of aged specimen with increase in concentration and temperature of sulphuric acid. With increase in concentration of sulphuric acid from 0.025 M to 0.25 M the corrosion rate of annealed sample was found to increase, but there after in 0.5 M, 0.75 M and 1 M, the rate of corrosion decreases, indicating passivation of alloy surface at higher concentration of sulphuric acid. The corrosion rate of aged specimen was found to be higher than that of the annealed specimen. Similar observations are revealed by SEM images. The thermodynamic parameters like activation energy, enthalpy of activation and entropy of activation were calculated.

Jayashree H.V.,PESIT | Thapliyal H.,USF | Agrawal V.K.,PESIT
Proceedings of the IEEE International Conference on VLSI Design | Year: 2014

Quantum computation is modeled by quantum circuits. All the quantum operations are reversible so the quantum circuits can be built using reversible logic gates. Reversible computing is the emerging technology, its major role is in the field of quantum computing, optical computing, and design of low power nanocircuits. The most frequently used computational unit for digital signal processing and multimedia applications is multiplier. To compute square of an operand, regular multipliers are used in general. This paper proposes a dedicated quantum circuit for computing square of an operand efficiently compared to the existing multipliers in the literature. The squaring unit is mathematically modeled and its metrics quantum cost, garbage outputs and ancilla input, gate count are calculated. We compared the proposed design with the existing multipliers to compute square and found that proposed square unit is efficient in terms of quantum cost, garbage outputs, ancilla inputs and gate count. The proposed reversible square circuit has 63% to 85% improvement of quantum cost, garbage outputs, ancilla inputs and gate count over existing reversible multiplier circuits. © 2014 IEEE.

Abhinandan K.R.,PESIT
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) | Year: 2013

In the current existing technology, literally everything is digital and machines are built and tuned to understand and respond to human gestures. In this paper, the human computer interaction platform is used for the treatment of the disorders, SHORT TERM MEMORY LOSS andANTEROGRADE AMNESIA. Victims of these disorders tend to forget stuffs after a short interval of time, but they have the ability to recover the lost memory and remember things, when a picture or a story or a scene relating to the lost memory incident is portrayed to them. This paper presents an idea of building a brain-computer interface to help the victims recover their lost memory by the visualization of the previously happened incident in a virtual frame. According to the theory proposed, the signals are extracted using Electroencephalography and conditioned for use in real world. These signals are stored in a processor and fed back to the brain to create a virtual vision so that the lost memory can be induced. © 2013 Springer-Verlag.

Retiming is a transformation which can be applied to digital filter blocks that can increase the clock frequency. This transformation requires computation of critical path and shortest path at various stages. In literature, this problem is addressed at multiple points. However, very little attention is given to path solver blocks in retiming transformation algorithm which takes up most of the computation time. In this paper, we address the problem of optimizing the speed of path solvers in retiming transformation by introducing high level synthesis of path solver algorithm architectures on FPGA and a computer aided design tool. Filters have their combination blocks as adders, multipliers, and delay elements. Avoiding costly multipliers is very much needed for filter hardware implementation. This can be achieved efficiently by using multiplierless MCM technique. In the present work, retiming which is a high level synthesis optimization method is combined with multiplierless filter implementations using MCM algorithm. It is seen that retiming multiplierless designs gives better performance in terms of operating frequency. This paper also compares various retiming techniques for multiplierless digital filter design with respect to VLSI performance metrics such as area, speed, and power. © 2014 Deepa Yagain and A. Vijaya Krishna.

Yagain D.,PESIT | Vijayakrishna A.,PESIT
Swarm and Evolutionary Computation | Year: 2015

In this paper, design of a new algorithm and a framework for retiming the DSP blocks based on evolutionary computation process is explained. Optimal DSP blocks such as digital filter design is a high level synthesis problem which includes optimally mapping digital filter specifications on to FPGA (Field Programmable Gate Array) architecture. Retiming is the considered optimization method in this paper which gives optimality in terms of algorithm processing speed and digital filter operating frequency with register count as a constraint. The designed novel algorithm is for the synthesis of high speed digital filters for different signal processing applications based on nature inspired evolutionary computation method. The classical retiming algorithms such as clock period minimization and register minimization that are addressed in the literature provide a single heuristic solution based on the chosen optimization parameter such as clock period. However, for retiming which is multi-objective optimization, evolutionary approach can lead to better results. Using the designed evolutionary computation based retiming method, retimed solution database is generated with higher frequency and different output register counts by searching the digital block solution space. Depending on the clock period and register count constraint, designer can take a design decision. Here, various signal processing designs are used to facilitate the design analysis. Results also show that the CPU processing time needed to compute multiple solutions using the designed algorithm for filter circuits is reduced for designs whose maximum feasible solutions are less than 50. If the circuit is very big with the possible solution space greater than 50 solutions, then algorithm performs slower. A comparison is also provided in the Simulations section with respect to all the existing classical retiming methods in the literature such as clock period and register minimization retiming to prove the concept. Multi-objective genetic algorithms are the considered evolutionary computation method in this paper. © 2014 Elsevier B.V. All rights reserved.

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