San Diego, CA, United States
San Diego, CA, United States

Peregrine Semiconductor is a San Diego-based manufacturer of high-performance RF CMOS integrated circuits. The company's products are used in aerospace and defense, broadband, industrial, mobile wireless device, test and measurement equipment and wireless infrastructure markets. Peregrine's UltraCMOS technology is a proprietary implementation of silicon on sapphire and silicon on insulator substrates that enables high levels of monolithic integration. Wikipedia.


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Patent
Peregrine Semiconductor | Date: 2017-01-04

A novel RF switch circuit and method for switching RF signals is described. The RF switch circuit is fabricated in a silicon-on-insulator (SOI) technology. The RF switch includes pairs of switching and shunting transistor groupings used to alternatively couple RF input signals to a common RF mode. The switching and shunting transistor grouping pairs are controlled by a switching control voltage (SW) and its inverse (SW). The switching and shunting transistor groupings comprise one or more MOSFET transistors connected together in a stacked or serial configuration. The stacking of transistor grouping devices, and associated gate resistors, increase the breakdown voltage across the series connected switch transistors and operate to improve RF switch compression. A fully integrated RF switch is described including digital control logic and a negative voltage generator integrated together with the RF switch elements. In one embodiment, the fully integrated RF switch includes a built-in oscillator, a charge pump circuit, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit. Several embodiments of the charge pump, level-shifting voltage divider, and RF buffer circuits are described. The inventive RF switch provides improvements in insertion loss, switch isolation, and switch compression.


Patent
Soitec and Peregrine Semiconductor | Date: 2017-03-22

The invention relates to a structure (100) for radiofrequency applications comprising:- a monocrystalline substrate (1),- a polycrystalline silicon layer (2) directly on the monocrystalline substrate (1),- an active layer (3) on the polycrystalline silicon layer (2), intended to receive radiofrequency components,characterized in that at least a first portion (2a) of the polycrystalline silicon layer (2) extending from the interface (I) of the polycrystalline silicon layer (2) with the monocrystalline layer includes carbon and/or nitrogen atoms located at the grain boundaries of the polycrystalline silicon. The invention further relates to a process for manufacturing such a structure.


Patent
Peregrine Semiconductor | Date: 2016-06-10

A DC-to-DC voltage converter comprising a differential charge pump that utilizes a differential clocking scheme to reduce output electrical noise by partial cancellation of charge pump glitches (voltage transients), and a corresponding method of operating a differential charge pump. The differential charge pump can be characterized as having at least two charge pump sections that initiate charge pumping in opposite phases of a clock signal to transfer (pump) charge to storage capacitors. The differential charge pump is particularly well suited for implementation in integrated circuit chips requiring negative and/or positive voltages, and multiples of such voltages, based on a single input voltage.


Patent
Peregrine Semiconductor | Date: 2016-09-02

An apparatus for selectively providing attenuation with minimal relative phase error. A Digital Step Attenuator (DSA) is implemented on an integrated circuit (IC). Each cell of the DSA has a series compensation inductance that is introduced between an input to the cell and a resistor on the cell. The series compensation inductance allows the location of a pole present in the transfer function of the cell to be manipulated. By controlling the location of the pole in the transfer function of the DSA, the relative phase error of the cell can be controlled. In another disclosed embodiment, the capacitance of a shunt compensation capacitor is increased to manipulate a pole in the transfer function of a DSA cell.


A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as stacked transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated.


Patent
Peregrine Semiconductor | Date: 2016-01-13

An RF switching device having distributed shunt switches distributed along transmission lines to improve RF bandwidth as well as the signal isolation of the device. The shunt switches may be physically positioned on both sides of the transmission lines to keep an integrated circuit (IC) design essentially symmetrical so as to provide predictable and reliable operational characteristics. Some embodiments include stacked FET shunt switches and series switches to tolerate high voltages. In some embodiments, the gate resistor for each FET shunt switch is divided into two or more portions.


Control systems and methods for power amplifiers operating in envelope tracking mode are presented. A set of corresponding functions and modules are described and various possible system configurations using such functions and modules are presented.


Patent
Peregrine Semiconductor | Date: 2016-02-19

A high performance integrated tunable impedance matching network with coupled merged inductors. Embodiments include a combination of merged multiport constructively coupled spiral inductors and tunable capacitors configured to reduce insertion losses, circuit size, and optimization time while maintaining a high Q factor for the coupled spiral inductors. Some embodiments integrate one or more filter circuits with a tunable impedance matching network, useful in conjunction with such applications as radio frequency power amplifiers.


Patent
Peregrine Semiconductor | Date: 2016-03-04

An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.


Patent
Peregrine Semiconductor | Date: 2016-03-02

Embodiments of signal bias generators and regulators are described generally herein. Other embodiments may be described and claimed.

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