Kumar S.,University of Seoul |
Park J.Y.,PDF Solutions Inc. |
Jung J.P.,University of Seoul
Electronic Materials Letters | Year: 2011
A high speed shear test for Sn-Ag-Cu(3. 0 wt %Sn and 0. 5 wt % Ag) solder has been studied by varying shearing rate, tip height and solder volume. Failure mode analysis of the solder joint revealed that ductile and brittle failure modes coexist when the shearingspeed is 500 mm/s or higher. The higher the shearing rate, the fewer the ductile failures and the more brittle or mixed failures have been observed. Tip height variation does not have astrong impact on failure mode, but occasions for pad lift appeared to be strongly related with tip height conditions. While the maximum shear force does not provide any indication of the failure mechanism, careful analysis of the force-displacement curves showed the potential of area related indices as a method to analyze the various failure modes. © 2011 The Korean Institute of Metals and Materials and Springer Netherlands.
Eisenmann H.,PDF Solutions Inc.
Proceedings of the International Symposium on Physical Design | Year: 2015
The placement significantly influences the quality of a circuit. In the past decades a lot of placement algorithms were presented. The most popular ones are summarized here. Force-directed placers are able to place VLSI circuits with low wirelength within a suitable time. Examples for force-directed placers are Kraftwerk and Kraftwerk2, which start with an initial placement and use forces to evenly distribute the modules inside the placement area.
PDF Solutions Inc. | Date: 2015-04-13
Computer software and hardware for use in providing automated characterization and analysis of product chip and cell library layouts in the field of semiconductor manufacturing.
Opportunistic Placement Of Ic Test Strucutres And/Or E-Beam Target Pads In Areas Otherwise Used For Filler Cells, Tap Cells, Decap Cells, Scribe Lines, And/Or Dummy Fill, As Well As Product Ic Chips Containing Same
PDF Solutions Inc. | Date: 2015-02-03
Product ICs/wafers include additional diagnostic, test, or monitoring structures opportunistically placed in filler cell positions, within tap cells, within decap cells, within scribe line areas, and/or within dummy fill regions. Improved fabrication processes utilize data from such structure(s) in wafer disposition decisions, rework decisions, process control, yield learning, or fault diagnosis.
PDF Solutions Inc. | Date: 2015-04-28
Semiconductor capital equipment namely, an electron beam inspection and metrology tool. Engineering and consulting services in the fields of semiconductor chip design and fabrication.