Agency: National Aeronautics and Space Administration | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 125.00K | Year: 2016
The proposed project aims to develop a 20GSps 6-bit radiation hardened analog to digital converter (ADC) required for microwave radiometers being developed for space and air borne earth sensing applications. Aiming to improve performance and to reduce the size of the electronics, high resolution, high-sampling rate, power efficiency and low spur energy are the requirements for ADCs employed for direct digitization in microwave radiometers. The proposed 20GS/s 6-bit interleaved successive approximation (SAR) ADC is intended to achieve >5 ENOB and 20GHz input bandwidth. A number of innovations will be introduced to the ADC in order to combine low power consumption with high signal to noise and distortion (SINAD), and spurious free dynamic range (SFDR) which is important for spectrography applications. A novel low glitch energy technique coupled with interleaved samples aperture calibration will be introduced to achieve digitization accuracy, improve linearity and achieve high sampling rate. The proposed ADC ASIC will contain on-chip all necessary components, including a frequency synthesizer, serial interface, standard interface with an FPGA, and design-for-testability features. The ADC will be implemented using a deep submicron CMOS technology. The project's Phase I will provide the proof of feasibility of implementing the proposed ADC. Phase II will include finishing design, fabrication, testing and delivering the ADC prototypes which will be ready for commercialization in Phase III.
Pacific Microchip Corporation and California Institute of Technology | Date: 2014-10-02
According to one embodiment, a cross-correlator comprises a plurality of analog front ends (AFEs), a cross-correlation circuit and a data serializer. Each of the AFEs comprises a variable gain amplifier (VGA) and a corresponding analog-to-digital converter (ADC) in which the VGA receives and modifies a unique analog signal associates with a measured analog radio frequency (RF) signal and the ADC produces digital data associated with the modified analog signal. Communicatively coupled to the AFEs, the cross-correlation circuit performs a cross-correlation operation on the digital data produced from different measured analog RF signals. The data serializer is communicatively coupled to the summing and cross-correlating matrix and continuously outputs a prescribed amount of the correlated digital data.
Agency: Department of Energy | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 145.41K | Year: 2012
The Facility for Rare Isotope Beams (FRIB) employs extremely complex instrument, involving thousands of detector elements that generate unprecedented amount of experimental data. Reliable extremely high data throughput standard compliant interfaces that consume low power and are capable of operation under harsh radiation conditions of nuclear physics experiments are required. Pacific Microchip Corp. proposes to design a 100Gbps Ethernet (100GbE) transceiver ASIC that meets the requirements of the IEEE 802.3ba standard and MSA specifications and supports both fiber optic and non-standard 10m copper 4x25Gbps interfaces. The proposed ASIC will be designed using RadHard methods, novel low power techniques and will be capable to operate over a wide temperature range. A novel ASIC feature will improve flip- flop radiation hardness when necessary, by increasing flip-flop power. The ASIC will be fabricated using deep submicron latchup free SOI CMOS technology. In Phase I, the novel ASIC architecture will be developed and modeled, the critical circuits will be designed and in silico proof of the concept will be provided. Phase II will result in the ASICs prototype being ready for commercialization in Phase III. Commercial applications and other benefits: In addition to the primary application in the data interfaces of FRIB detectors and other nuclear physics instruments such as CMS and ATLAS at LHC, the proposed transceiver ASIC will find application in 100GbE modules and line cards (SMF and MMF media), DP-QPSK based long- haul single-wavelength 100GbE interfaces and low-cost low-power transmission of 4X25Gbps format data over 10m copper media for server inter/intro rack/cabinet interface.
Agency: National Aeronautics and Space Administration | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 125.00K | Year: 2014
The proposed project aims to develop a multi-channel analog to digital converter (ADC) required for a fluxgate magnetometer (EPD) employed on NASA's planetary exploration missions. The ADC has to feature very high resolution, radiation hardness (tolerance to SEE and TID), low power consumption and be suitable for operation over a wide temperature range. The proposed 3-channel sigma-delta ADC will be a wide-tunable device which will achieve resolution from 17 to 23.5 effective number of bits (ENOB) at 51.2kS/s rate. The combination of the innovative reconfigurable architecture and low distortion topology will permit to optimize the ADC's power consumption within a wide range and to ensure 3.5fJ figure of merit (FoM). The offset cancellation technique will be implemented to the ADC to solve the offset problem common to all magnetometers. Radiation hardening techniques such as RHBD, RHBL and RHBS will be employed. The proposed novel 17-level sub-ADC's topology requires two times fewer comparators than classic topology, which also helps to save power and to reduce the on-chip area. The ADC will be implemented using IBM's deep submicron SOI CMOS technology with connected body option. Phase I work will provide the proof of feasibility of implementing the proposed ADC. Phase II will result in the silicon proven ADC's prototypes being ready for commercialization in Phase III.
Agency: National Aeronautics and Space Administration | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 125.00K | Year: 2014
The NASA's PATH mission employs a synthetic aperture radiometer that produces 768 IF (10MHz - 500MHz) signals. Digitizing the signals results in 1.536Tb/s (1GS/s, 2-bit) data stream. Within the NASA's SBIR contracts NNX12CE50P and NNX13CP01C, Pacific Microchip Corp. has developed a low power 64x64 cross-correlator ASIC offering the reduction of the amount of data to manageable levels. This ASIC includes an array of 128 digitizers operated at 1GS/s and 2-bit precision. This ASIC is the key component in the proposed cross-correlator system for the PATH mission. The innovation offers to greatly reduce the power consumption, weight and the system's complexity. Phase I will demonstrate the feasibility of implementation of the system based on the developed ASIC. We will design the cross-correlator system's schematic, its behavioral model and will run the simulations proving the requirements of the PATH mission can be met. The PCB will also be designed to prove the feasibility of the system's physical implementation and meeting electrical and thermal requirements. Phase II will result in the complete system's assembly, its electrical and thermal characterization and validation on the PATH's radiometer which is being developed at JPL.
Agency: National Aeronautics and Space Administration | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 124.97K | Year: 2012
NASA's latest effort in developing a common platform for space communication and navigation systems is the Space Telecommunications Radio System (STRS) standard. It defines architecture enabling interoperability of Software Defined Radio (SDR) components. Future proof, power conscious architectures of STRS compliant re-configurable SDR transceivers are needed for implementation of envisioned space communication systems.Pacific Microchip Corp. proposes to develop a highly integrated, low-power, multifunctional 56GS/s Direct Digital Modulation/Demodulation (DDM) SDR transceiver using 45nm SOI CMOS technology. The resulting STRS compliant integrated solution will be radiation tolerant by technology and design. The direct conversion based transceiver utilizes novel 56GS/s D/A and A/D converters and features arbitrary waveform generation (AWG) mode. The availability of AWG and DDM modes removes limitations on the synthesized waveform shapes up to 28GHz. Pacific Microchip Corp. proposes all-digital implementation of frequency up- and down-conversion, I/Q modulation and demodulation. Since digital power is mostly dynamic, digital processing will enable power consumption scaling linearly with the operating frequency.Phase I work will provide a complete definition and in-silico validation of the proposed device. The Phase II program will produce a fieldable product. In order to facilitate the commercialization efforts in Phase III, a commercial radiation-tolerant CMOS SOI technology will be used.
Agency: National Aeronautics and Space Administration | Branch: | Program: SBIR | Phase: Phase II | Award Amount: 750.00K | Year: 2015
The measurement of the magnetic field vector is of fundamental importance to space physics missions. The fluxgate magnetometer is a device developed for precise vector measurement of static magnetic fields. The high performance magnetometers are required in such NASA missions as ICON, GOLD, Solar Orbiter, Solar Probe Plus, ONEP, SEPAT, INCA, CISR, DGC, HMag and other planetary explorations. The analog-to-digital converter (ADC) is one of the critical components of the magnetometer. The performance of the magnetometer directly depends on the ADC's characteristics such as the resolution, accuracy, and conversion speed. The general requirements for all ADCs used in space missions are low power consumption, low area, and high radiation tolerance. Pacific Microchip Corp. proposes to develop a rad-hard ADC specifically targeted for application in Fluxgate Magnetometers. Phase I work provided a proof of feasibility, complete definition and validation based on extensive simulation and analysis of the proposed ADC. During Phase II the ADC design will be finished, the ADC will be fabricated, packaged and tested (including radiation hardiness). At the end of Phase II a fieldable product will be produced. In order to facilitate the commercialization efforts in Phase III, the product will be fabricated using a commercial 180nm CMOS technology.
Agency: National Aeronautics and Space Administration | Branch: | Program: SBIR | Phase: Phase II | Award Amount: 1.50M | Year: 2015
The NASA's PATH mission employs GeoSTAR spectral radiometer processing data from antenna consisting of three arms, each holding 128 microwave receivers. Each of the 384 receivers amplifies RF signals, and down-converts them to an intermediate frequency (IF). As a result, 768 in-phase (I) and quadrature (Q) signals are produced with a frequency of 10 to 500MHz. The IF signals have to be normalized and digitized with 1Gs/s sampling rate for further cross-correlation. Each signal from one arm of the receiver must be cross-correlated with all signals from the other two arms, therefore a system containing 196,000 parallel cross-correlation blocks is needed. Since the GeoSTAR is a space born instrument, low power dissipation and ensuring system reliability, through processing redundancy, are one of the most important requirements. A system assembled by using off-the-shelf components would be extremely power inefficient, bulky, and unreliable. Therefore, a system that is based on application specific integrated circuits (ASICs) is required. While working on the NASA's SBIR Phase II project "Low Power Cross-Correlator ASIC" (NNX13CP01C), Pacific Microchip Corp. has developed and fabricated an ASIC that includes 128-element array of 2-bit 1GS/s ADCs, and 4096 parallel cross-correlation cells. The ASIC was designed based on the GeoSTAR radiometer requirements, therefore it is intended to be the key component in the cross-correlator system which is being developed. The system will contain means correlation results further post-processing and control of ASICs.
Agency: Department of Energy | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 155.00K | Year: 2016
The large-scale detectors that are used in nuclear physics (NP) experiments undergo upgrades leading to increasingly high-density readout electronics, producing extremely large amounts of data. For example, the 12GeV luminosity upgrade related GlueX Program at Jefferson Lab Hall-D projects raw data volume to reach 2300TB/s in 2018. To accommodate the transmission of the increasingly high data volumes within the NP detector facilities, additional or new optic fiber has to be deployed, which in turn leads to additional effort and cost. Pacific Microchip Corp. proposes to develop a 100Gb/s transceiver ASIC, which will be collecting ten data streams at up to 10Gb/s (the usual data rate within the NP facilities), serializing them to the standard 100Gb/s data format and transmitting using already existing fiber. As a result, the data throughput will be increased by an order circumventing the effort, hassle and cost associated with replacing the fiber optic media. In Phase I, the novel ASIC’s architecture will be developed and modeled, the critical circuits will be designed and the proof of the concept based on computer simulations will be provided. Phase II will result in the fabricated and tested prototype of the ASIC and the data link being prepared for commercialization in Phase III. This project will develop a 100Gbps transceiver ASIC for upgrading 10Gb/s fiber optic links to 100Gb/s without upgrading the optic fiber. The transceiver ASIC will facilitate 10 times increase of the data throughput within NP facilities such as the Jefferson Lab Hall-D without re-deploying the optic fiber. Commercial Applications and Other Benefits: In addition to the primary application of the proposed transceiver ASIC for increase of data throughput in NP detector facilities such as the Jefferson Lab Hall-D, the proposed 100Gbps transceiver has a huge market in 100GbE and 400GbE transceiver modules and line cards for data transmission over long and short hole fiber optic networks. Since the proposed ASIC needs a single wavelength and single polarization mode and it does not require optic fiber upgrade to transmit at 100Gb/s, we expect a huge demand for the ASIC and commercialization success.
Agency: National Aeronautics and Space Administration | Branch: | Program: SBIR | Phase: Phase II | Award Amount: 950.00K | Year: 2013
The NASA's PATH mission includes the GeoSTAR satellite that carries aboard a microwave sounder employing an array of 375 microwave antennas with corresponding receivers. Each receiver is tuned to the 180GHz frequency, while the intermediate frequency (IF) reaches 500MHz. The IF signal is quantized at 1GHz with 2-bit accuracy. The resulting data rate is 700Gb/s. This data has to be pre-processed aboard the satellite before it can be transmitted to Earth for further processing. One of the steps of such data processing is cross-correlation. For a space borne instrument, power dissipation and radiation hardness are among the most important requirements. Pacific Microchip Corp. is designing an ASIC that includes a cross-correlation unit with interfaces for the GeoSTAR's receivers. The ASIC will have greatly reduced power consumption compared to that of the FPGA-based or classic ASIC-based implementations. This ASIC must be designed and integrated with already existing system components of the GeoSTAR instrument. The ASIC includes cross-correlation cells based on novel architecture. The deep submicron SOI CMOS technology selected for the ASIC's fabrication will increase its tolerance to the total ionizing dose (TID) and reduce the probability of radiation-induced latch-up. The design of the ASIC will follow design for testability (DFT) methods, which will simplify characterization and testing of the fabricated ASIC, reduce risk and lower the cost of the product.