Limeil-Brévannes, France
Limeil-Brévannes, France

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Patent
Ommic | Date: 2015-03-10

A process for fabricating a heterojunction field-effect transistor including a semiconductor structure made up of superposed layers, including: providing on a substrate layer (1) a buffer layer (2), a channel layer (3) and a barrier layer (4), the layers being made of materials having hexagonal crystal structures of the Ga_((1-p-q))Al_((p))In_((q))N type; forming an opening in a dielectric masking layer (5) deposited on the barrier layer; growing by high-temperature epitaxy a semiconductor material (6, 6) having a hexagonal crystal structure, namely Ga_((1-x-y))Al_((x))In_((y))N, doped with germanium, on a growth zone defined by the opening formed in the masking layer; and depositing a source or drain contact electrode (15, 16) on the material thus deposited by epitaxy, and a gate electrode (13) in a location outside of the growth zone.


Olomo A.,OMMIC | Olomo A.,Infineon Technologies
EuMIC 2016 - 11th European Microwave Integrated Circuits Conference | Year: 2016

In this work, a new Ids current equation and FET model are proposed. This model is extracted from CW and pulsed measurements. Pulsed measurements are used to separate trapping and thermal effects. From these measurements, a trapping circuit model is determined and implemented. Thermal effects, due to power dissipation of the device, are also included. The dispersive effect is handled dynamically and does not require to compute separately the bias point of the transistor. Comparison between measured and simulated results will prove its validity under both CW and dynamic conditions. © 2016 European Microwave Association.


Patent
Ommic | Date: 2017-01-18

The invention relates to a method for manufacturing a heterojunction field-effect transistor. Said transistor includes a semiconductor structure made of stacked layers. Said method includes: providing a buffer layer (2), a channel layer (3), and a barrier layer (4) on a substrate layer (1), which are all produced with Ga(1-p-q)Al(p)In(q)N hexagonal crystal materials; forming an opening in a dielectric masking layer (5) deposited on the barrier layer; growing, using high-temperature epitaxy, a Germanium-doped Ga(1-X-y)Al(X)In(y)N hexagonal crystal semiconductor material (6, 6) on a growth area defined by the opening formed in the masking layer; and depositing a source or drain contact electrode (15, 16) onto the material, thus deposited via epitaxy, and depositing a gate electrode (13) at a location outside the growth area.


Frayssinet E.,French National Center for Scientific Research | Cordier Y.,French National Center for Scientific Research | Schenk H.P.D.,PICOGIGA International | Bavard A.,OMMIC
Physica Status Solidi (C) Current Topics in Solid State Physics | Year: 2011

In this paper, we report on the growth of thick gallium nitride (GaN) layers on 4-in. and 6-in., (111)-orientated silicon substrates by metalorganic vapor phase epitaxy. Up to 4 μm thick continuous GaN layers have been obtained by inserting both SiN and AlN interlayers into the structure. With dislocation densities of about 1-2×109 cm-2 and GaN(002) and (302) X-ray rocking curve full widths at half maximum of 420 and 1360 arcsec for 4-in. and 374 and 810 arcsec for 6-in., respectively, the final continuous GaN layer exhibits excellent crystalline properties. © 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.


Schenk H.P.D.,PICOGIGA International | Schenk H.P.D.,French National Center for Scientific Research | Frayssinet E.,French National Center for Scientific Research | Bavard A.,OMMIC | And 3 more authors.
Journal of Crystal Growth | Year: 2011

We report on the growth of thick GaN epilayers on 4-in. Si(1 1 1) substrates by metalorganic chemical vapor deposition. Using intercalated AlN layers that contribute to counterbalance the tensile strain induced by the thermal mismatch between gallium nitride and the silicon substrate, up to 6.7 μm thick crack-free group III-nitride layers have been grown. Root mean-squares surface roughness of 0.5 nm, threading dislocation densities of 1.1×109 cm-2, as well as X-ray diffraction (XRD) full widths at half-maximum (FWHM) of 406 arcsec for the GaN(0 0 2) and of 1148 arcsec for the GaN(3 0 2) reflection have been measured. The donor bound exciton has a low-temperature photoluminescence line width of 12 meV. The correlation between the threading dislocation density and XRD FWHM, as well as the correlation between the wafer curvature and the GaN in-plane stress is discussed. An increase of the tensile stress is observed upon n-type doping of GaN by silicon. © 2010 Elsevier B.V. All rights reserved.


Patent
Soitec, Ommic and French National Center for Scientific Research | Date: 2012-06-28

The invention relates to a method for manufacturing, by means of epitaxy, a monocrystalline layer of GaN on a substrate, wherein the coefficient of thermal expansion is less than the coefficient of thermal expansion of GaN, comprising the following steps: (b) three-dimensional epitaxial growth of a layer of GaN relaxed at the epitaxial temperature, (c1) growth of an intermediate layer of B_(w)Al_(x)Ga_(y)In_(z)N, growth of a layer of B_(w)Al_(x)Ga_(y)In_(z)N, (c3) growth of an intermediate layer of B_(w)Al_(x)Ga_(y)In_(z)N, at least one of the layers formed in steps (c1) to (c3) being an at least ternary III-N alloy comprising aluminium and gallium, (d) growth of said layer of GaN.


Akgiray A.H.,California Institute of Technology | Weinreb S.,California Institute of Technology | Leblanc R.,OMMIC | Renvoise M.,OMMIC | And 3 more authors.
IEEE Transactions on Microwave Theory and Techniques | Year: 2013

The noise models of InP and GaAs HEMTs are compared with measurements at both 300 and 20 K. The critical parameter, Tdrain, in the Pospieszalski noise model is determined as a function of drain current by measurements of the 1-GHz noise of discrete transistors with 50-Ω generator impedance. The dc I-V for the transistors under test are presented and effects of impact-ionization are noted. InP devices with both 100% and 75% indium mole fraction in channel are included. Examples of the design and measurement of very wideband low-noise amplifiers (LNAs) using the tested transistors are presented. At 20-K physical temperature the GaAs LNA achieves <10-K noise over the 0.7-16-GHz range with 16 mW of power and an InP LNA measures <20-K noise over the 6-50-GHz range with 30 mW of power. © 1963-2012 IEEE.


Bouzid-Driad S.,OMMIC | Bouzid-Driad S.,Institute for Electronics | Maher H.,OMMIC | Defrance N.,Institute for Electronics | And 4 more authors.
IEEE Electron Device Letters | Year: 2013

This letter reports on AlGaN/GaN high-electron-mobility transistors (HEMTs) on high-resistive silicon substrate with a record maximum oscillation cutoff frequency FMAX. Double-T-shaped gates are associated with an optimized technology to enable high-efficiency 2-D electron gas control while mitigating the parasitic resistances. Good results of FMAX = 206 GHz and FT100 GHz are obtained for a 90-nm gate-length HEMT with 0.25-μ m source-to-gate spacing. The associated peak extrinsic transconductance value is as high as 440 mS mm-1. To the authors' knowledge, the obtained FMAX and Gmext are the highest reported values for GaN HEMTs technology on silicon substrate. The accuracy of the cutoff frequency values is checked by small-signal modeling based on extracted S-parameters. © 2012 IEEE.


Zaknoune M.,CNRS Institute of Electronics, Microelectronics and Nanotechnology | Mairiaux E.,CNRS Institute of Electronics, Microelectronics and Nanotechnology | Roelens Y.,CNRS Institute of Electronics, Microelectronics and Nanotechnology | Waldhoff N.,CNRS Institute of Electronics, Microelectronics and Nanotechnology | And 4 more authors.
IEEE Electron Device Letters | Year: 2012

Self-aligned 0.55× 3.5 μl m 2 emitter InP/GaAsSb/InP double heterojunction bipolar transistors demonstrating an f t of 310 GHz and an f max of 480 GHz are reported. Common-emitter current gain of 24, together with a breakdown voltage of 4.6 V, is measured. The devices were fabricated with a triple-mesa process and easily fabricated with a new base isolation μ-airbridge design which, moreover, significantly reduced the base-collector capacitance C BC. © 2012 IEEE.


Ciccognani W.,University of Rome Tor Vergata | Limiti E.,University of Rome Tor Vergata | Longhi P.E.,ELT Elettronica SpA | Renvoise M.,OMMIC
IEEE Journal of Solid-State Circuits | Year: 2010

Radioastronomy applications, as well as others, require ultra-low-noise front ends for high-sensitivity receivers. In this way, the image produced from a radio-telescope using such advanced components has a higher resolution and therefore allows scientists to obtain a clearer representation of the environment. The low-noise amplifier is the key component of a high sensitivity receiver (demonstrating a very low noise figure, even in the millimeter-wave frequency region). Such electrical performance is obtained from the combined use of an advanced technology (fT and fmax > 250 GHz, LG, < 0, 1 μm) and appropriate design methodologies that take into account electrical specifications and system constraints in the context of the targeted application. In this contribution, we will present both the performance of the employed technology (OMMIC 70 nm GaAs mHEMT) and the related low-noise design methodologies that have led to the realization of four different LNAs operating from 5 GHz up to 100 GHz and beyond. © 2006 IEEE.

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