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Mansfield, CT, United States

Grant
Agency: Department of Defense | Branch: Missile Defense Agency | Program: SBIR | Phase: Phase I | Award Amount: 99.85K | Year: 2008

Phased arrays radars can expect considerable improvements with RF photonics. Current TR modules use numerous MMIC chips, ferrite circulators and phase shifters and quasi-optical true-time-delay (TTD). Transmission power distribution and synchronization across multiple RF interfaces can be improved. Large scale integration could address the problem of interconnecting boards with GHZ RF outputs but currently is not possible. Such integration with optical control will be a key enabling technology. ODIS proposes a monolithic IC solution based upon novel optoelectronic (OE) thryistor circuit design. Thyristor/HFET circuits implement a novel power amplifier using a gated OE oscillator driving a Class E output. The receive channel is implemented with an photonic link based upon linear phase modulation and coherent detection which achieves an SFDR of -92dB and SNR of -149dB. The photonic receive link also implements narrow channel microwave filtering in the optical domain. The photonic technology also enables novel AD architectures for the back end conversion or for direct digitization after the LNA. The photonic insertion is in the form of monolithic integrated circuits and the fabrication technology includes high temperature (850C) processing which pre-qualifies it for the mil-spec environment. Elimination of oxides results in rad-hard circuits. The in-plane photonics simplifies the package.


Grant
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase I | Award Amount: 99.99K | Year: 2009

Optical switching fabrics (optical cross-connects) require arrays of highly interconnected optical switching devices. Such fabrics require a high density of optical and electronic interconnect.  The optical switching devices are also required to switch configurations in sub-ns time intervals to enable reconfiguration times between packets that introduce little if any latency. Currently such fabrics do not exist commercially (8x8 demonstrated) and all routing is done with circuit switched architectures.  Possible candidates include MEMS mirror arrays, electro-optic switches, interferometric switches, digital optical switches, liquid crystal switches, bubble switches, acoustooptic switches  and semiconductor amplifier switches. The issues are insertion loss, crosstalk, extinction ratio, polarization dependence and scalability. The only approach with high speed potential is the electro-optic switch. The only electro-optic switch with small size and scalability is the semiconductor based directional coupler. The only semiconductor directional coupler that can be scaled to lengths


Grant
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase I | Award Amount: 99.99K | Year: 2009

The digital signal processor is currently dominated exclusively by CMOS technology. This is largely due to the fact that it is the only low power (VLSI density) technology available. However, CMOS is near the end of its scaling potential and it has a severe liability for space applications due to a weakness to radiation.  Recent progress in integrated optoelectronics has indicated dramatic performance improvements in clock and data recovery and in the mux/demux operations are possible. This may also apply to digital logic functions. For example the basic flip flop function could be implemented with EO devices activated by optical signals and producing optical outputs.  Such approaches could reduce the number of devices and the power while simultaneously increasing the speed. ODIS proposes a new technology base to enable this digital flip flop implementation. The latching function is provided by an EO thyristor which produces laser light in the on state. Optically activated transistors control the switching functions. This approach is compatible with optical signal transport, with on chip optical clock generation and timing control and with optical I/O. In this work, ODIS will develop J-K flip flops and their related synchronous circuits based on a new GaAs optoelectronic integration platform. BENEFIT: The digital processor market is several billion dollars with steady growth potential based upon an expending PC industry. As CMOS is constrained by power and speed , the opportunity for GaAs based circuits is significant. The wireless industry is already using all of the GaAs amplifiers that are produced. One can therefore expect a market opportunity for GaAs based digital products with large up-side potential. Digital products can now be added to a growing number of markets addressed by integrated optoelectronics  including AD converters, imager products, parallel optical data links, optical interface circuits, phased array receivers and other markets currently dominated by Si.


Grant
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase I | Award Amount: 99.89K | Year: 2010

The digital signal processing and static memory is currently dominated exclusively by CMOS technology with the 6-T cell implementing all static memory. CMOS is the only VLSI technology. However, CMOS is near the end of its scaling potential and it has a severe liability for space applications due to a weakness to radiation. Further, the 6T cell is relatively area and power consumptive and falls well short of the requirements for next generation satellites. ODIS proposes an optoelectronic solution based upon a monolithic technology platform for O and E devices. A key element in the device group is the thyristor which has both laser and detector functions. The thyristor has a very low power storage mode that enables a single device memory cell that may be dynamic or a static memory cell. The dynamic version offers the lowest possible power of any known semiconductor memory. Both the read and write operations are performed optically with on-chip light sources enabling very high speed and high density memory arrays. In addition to the ultra-low power memory , the thyristor also enables a low power logic gate. In this SBIR, ODIS will demonstrate the first integrated low power dynamic ram and logic cell BENEFIT: The digital processor market is several billion dollars with steady growth potential based upon an expending PC industry. As CMOS is constrained by power and speed , the opportunity for GaAs based circuits is significant. The wireless industry is already using all of the GaAs amplifiers that are produced. One can therefore expect a market opportunity for GaAs based memory products with large up-side potential. Digital products can now be added to a growing number of markets addressed by integrated optoelectronics including AD converters, imager products, parallel optical data links, optical interface circuits, phased array receivers and other markets currently dominated by Si.


Grant
Agency: Department of Defense | Branch: Navy | Program: SBIR | Phase: Phase I | Award Amount: 79.94K | Year: 2010

CDMA is a successful network technology for the wireless industry which relies totally on conventional integrated circuits. The same architecture is equally appealing for telecommunications and is considered an optimum choice for next generation FTTH networks if only low cost implementations were available. The persistent high costs are driven by disparity between optical and electrical components which include WDM capability on the one hand and digital processing on the other. What is required is the ability to merge these onto a single integrated platform so that signals could remain optical at high speeds right to the point that OE conversion was essential. With both capabilities on one die, cost goes down and performance goes up. These same attributes apply to airborne communications. The security enabled is a key aspect and thus multiple recent efforts have focused on the addition of existing PIC devices to a standard CMOS platform. ODIS offers a different solution in the form of POET, a III-V complementary HFET technology on the same integrated circuit as the wavelength division components for OCDMA. This approach achieves the goal and has already solved the main issue of technology compatibility. In this SBIR , POET will be demonstrated for OCDMA.

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