Nova Measuring Instruments is a publicly traded company, headquartered in Israel, that designs, develops and produces monitoring and measurement systems for the semiconductor manufacturing industry. Shares of the company are traded on the NASDAQ Global Market and on the Tel Aviv Stock Exchange. Wikipedia.
Nova Measuring Instruments | Date: 2015-07-14
An inspection system and method are presented for inspecting structures having a pattern formed by an array of elongated grooves having high aspect-ratio geometry, such as semiconductor wafers formed with vias. The inspection system comprises an imaging system and a control unit. The imaging system is configured and operable for imaging the structure with a dark-field imaging scheme and generating a dark-field image. The control unit comprises an analyzer module for analyzing pixels brightness in the dark-field image for identifying a defective groove, being a groove characterized by pixels brightness in the dark-field image lower than nominal brightness by a predetermined factor.
Nova Measuring Instruments | Date: 2017-02-13
A method of controlling a manufacturing process, the method including the steps of a) providing a testing area with a periodic structure, where the periodic structure includes a series of sets of patterned features, b) illuminating the periodic structure with a light, thereby producing a non-zero order diffraction signal, c) collecting the diffraction signal to produce a test signature, d) matching the test signature with a reference signature, where the reference signature was previously produced by performing steps a), b), and c) with respect to a reference structure that is at least similar to the periodic structure, and e) controlling a manufacturing process using a control setting set associated with the matching reference signature.
Nova Measuring Instruments | Date: 2015-06-18
A test structure is presented for use in metrology measurements of a sample pattern formed by periodicity of unit cells, each formed of pattern features arranged in a spaced-apart relationship along a pattern axis. The test structure comprises a test pattern, which is formed by a main pattern which includes main pattern features of one or more of the unit cells and has a symmetry plane, and a predetermined auxiliary pattern including at least two spaced apart auxiliary features located within at least some features of the main pattern, parameters of which are to be controlled during metrology measurements.
Nova Measuring Instruments | Date: 2015-02-16
A sample comprising an overlay target is presented. The overlay target comprises at least one pair of patterned structures, the patterned structures of the pair being accommodated in respectively bottom and top layers of the sample with a certain vertical distance h between them, wherein a pattern in at least one of the patterned structures has at least one pattern parameter optimized for a predetermined optical overlay measurement scheme with a predetermined wavelength range.
Nova Measuring Instruments | Date: 2016-10-05
A control system and method are provided for use in managing optical measurements on target structures. The control system comprises: data input utility for receiving input data indicative of a size of a target structure to be measured and input data indicative of illumination and collection channels of an optical measurement system; data processing utility for analyzing the input data, and an interplay of Point Spread Functions (PSFs) of the illumination and collection channels, and determining data indicative of optional tailoring of apertures to be used in the optical measurement system for optimizing ensquared energy for measurements on the given target structure, the optimal tailoring composing at least one of the following: an optimal ratio between numerical apertures of the illumination and collection channels; and an optimal orientation offset of physical apertures in the illumination and collection channels.
Nova Measuring Instruments | Date: 2016-12-20
A method and system are presented for use in controlling a process applied to a patterned structure having regions of different layered stacks. The method comprises: sequentially receiving measured data indicative of optical response of the structure being processed during a predetermined processing time, and generating a corresponding sequence of data pieces measured over time; and analyzing and processing the sequence of the data pieces and determining at least one main parameter of the structure. The analyzing and processing comprises: processing a part of said sequence of the data pieces and obtaining data indicative of one or more parameters of the structure; utilizing said data indicative of said one or more parameters of the structure and optimizing model data describing a relation between an optical response of the structure and one or more parameters of the structure; utilizing the optimized model data for processing at least a part of the sequence of the measured data pieces, and determining at least one parameters of the structure characterizing said process applied to the structure, and generating data indicative thereof.
Agency: European Commission | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-02-2014 | Award Amount: 139.30M | Year: 2015
The proposed pilot line project WAYTOGO FAST objective is to leverage Europe leadership in Fully Depleted Silicon on Insulator technology (FDSOI) so as to compete in leading edge technology at node 14nm and beyond preparing as well the following node transistor architecture. Europe is at the root of this breakthrough technology in More Moore law. The project aims at establishing a distributed pilot line between 2 companies: - Soitec for the fabrication of advanced engineered substrates (UTBB: Ultra Thin Body and BOx (buried oxide)) without and with strained silicon top film. - STMicroelectronics for the development and industrialization of state of the art FDSOI technology platform at 14nm and beyond with an industry competitive Power-Performance-Area-Cost (PPAC) trade-off. The project represents the first phase of a 2 phase program aiming at establishing a 10nm FDSOI technology for 2018-19. A strong added value network is created across this project to enhance a competitive European value chain on a European breakthrough and prepare next big wave of electronic devices. The consortium gathers a large group of partners: academics/institutes, equipment and substrate providers, semiconductor companies, a foundry, EDA providers, IP providers, fabless design houses, and a system manufacturer. E&M will contribute to the objective of installing a pilot line capable of manufacturing both advanced SOI substrates and FDSOI CMOS integrated circuits at 14nm and beyond. Design houses and electronics system manufacturer will provide demonstrator and enabling IP, to spread the FDSOI technology and establish it as a standard in term of leading edge energy efficient CMOS technology for a wide range of applications battery operated (consumer , healthcare, Internet of things) or not. Close collaboration between the design activities and the technology definition will tailor the PPAC trade-off of the next generation of technology to the applications needs.
Agency: European Commission | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-15-2015 | Award Amount: 150.05M | Year: 2016
The TAKE5 project is the next in a chain of thematically connected ENIAC JU KET pilot line projects which are associated with 450mm/300mm development for the 10nm technology node and the ECSEL JU project SeNaTe aiming at the 7nm technology node. The main objective of the TAKE5 project is the demonstration of 5nm patterning in line with the industry needs and the ITRS roadmap in the Advanced Patterning Center at the imec pilot line using innovative design and technology co-optimization, layout and device architecture exploration, and comprising demonstration of a lithographic platform for EUV technology, advanced process and holistic metrology platforms and new materials. A lithography scanner will be developed based on EUV technology to achieve the 5nm module patterning specification. Metrology platforms need to be qualified for 5nm patterning of 1D, 2D and 3D geometries with the appropriate precision and accuracy. For the 5nm technology modules new materials will need to be introduced. Introduction of these new materials brings challenges for all involved deposition processes and the related equipment set. Next to new deposition processes also the interaction of the involved materials with subsequent etch steps will be studied. The project will be dedicated to find the best options for patterning. The project relates to the ECSEL work program topic Process technologies More Moore. It addresses and targets as set out in the MASP at the discovery of new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the nano-structuring of electronic devices with 5nm resolution in high-volume manufacturing and fast prototyping. The project touches the core of the continuation of Moores law which has celebrated its 50th anniversary and covers all aspects of 5nm patterning development.
Agency: European Commission | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-02-2014 | Award Amount: 181.08M | Year: 2015
The SeNaTe project is the next in a chain of thematically connected ENIAC JU KET pilot line projects which are associated with 450mm/300mm development for the 12nm and 10nm technology nodes. The main objective is the demonstration of the 7nm IC technology integration in line with the industry needs and the ITRS roadmap on real devices in the Advanced Patterning Center at imec using innovative device architecture and comprising demonstration of a lithographic platform for EUV and immersion technology, advanced process and holistic metrology platforms, new materials and mask infrastructure. A lithography scanner will be developed based on EUV technology to achieve the 7nm module patterning specification. Metrology platforms need to be qualified for N7s 1D, 2D and 3D geometries with the appropriate precision and accuracy. For the 7nm technology modules a large number of new materials will need to be introduced. The introduction of these new materials brings challenges for all involved processes and the related equipment set. Next to new deposition processes also the interaction of the involved materials with subsequent etch, clean and planarization steps will be studied. Major European stakeholders in EUV mask development will collaboratively work together on a number of key remaining EUV mask issues. The first two years of the project will be dedicated to find the best options for patterning, device performance, and integration. In the last year a full N7 integration with electrical measurements will be performed to enable the validation of the 7nm process options for a High Volume Manufacturing. The SeNaTe project relates to the ECSEL work program topic Process technologies More Moore. It addresses and targets as set out in the MASP at the discovery of new Semiconductor Process, Equipment and Materials solutions for advanced CMOS processes that enable the nano-structuring of electronic devices with 7nm resolution in high-volume manufacturing and fast prototyping.
Agency: European Commission | Branch: H2020 | Program: ECSEL-RIA | Phase: ECSEL-06-2015 | Award Amount: 23.11M | Year: 2016
The objective of the 3DAM project is to develop a new generation of metrology and characterization tools and methodologies enabling the development of the next semiconductor technology nodes. As nano-electronics technology is moving beyond the boundaries of (strained) silicon in planar or finFETs, new 3D device architectures and new materials bring major metrology and characterization challenges which cannot be met by pushing the present techniques to their limits. 3DAM will be a path-finding project which supports and complements several existing and future ECSEL pilot-line projects and is linked to the MASP area 7.1 (subsection More Moore). Innovative demonstrators and methodologies will be built and evaluated within the themes of metrology and characterization of 3D device architectures and new materials, across the full IC manufacturing cycle from Front to Back-End-Of-Line. 3D structural metrology and defect analysis techniques will be developed and correlated to address challenges around 3D CD, strain and crystal defects at the nm scale. 3D compositional analysis and electrical properties will be investigated with special attention to interfaces, alloys and 2D materials. The project will develop new workflows combining different technologies for more reliable and faster results; fit for use in future semiconductor processes. The consortium includes major European semiconductor equipment companies in the area of metrology and characterization. The link to future needs of the industry, as well as critical evaluation of concepts and demonstrators, is ensured by the participation of IMEC and LETI. The project will directly increase the competitiveness of the strong Europe-based semiconductor Equipment industry. Closely connected European IC manufacturers will benefit by accelerated R&D and process ramp-up. The project will generate technologies essential for future semiconductor processes and for the applications enabled by the new technology nodes.