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New Orleans, LA, United States

A lens system comprises, on a side closest to an object, a first lens component having a positive refractive power and a second lens component having a positive refractive power in order from the object; and on a side closest to an image, a cemented lens constructed by cementing together a positive lens and a negative lens in order from the object; wherein the lens system satisfies the following conditional expressions: where n1 and 1 denote a refractive index and an Abbe number of the first lens component at d-line, respectively, and n2 and 2 denote a refractive index and an Abbe number of the second lens component at d-line, respectively.


A secondary side synchronous rectification control circuit is disclosed. The control circuit includes an inverted amplifier, a first comparator, and a driving unit. The inverted amplifier has an input end for receiving a drain source voltage signal from a synchronous rectification transistor and outputting an inverted amplification signal. The first comparator receives the inverted amplification signal and a first reference voltage for outputting a first comparison signal. The driving unit receives the first comparison signal and generates a driving signal according to the first comparison signal, for controlling the conduction status of the synchronous rectification transistor. The drain source voltage of the synchronous rectification transistor in the present invention is inverted amplified by an inverted amplifier, and it is connected to a comparator for generating the driving signal. The errors and defects of the turn-off timing of the driving signal may be solved and eliminated.


Patent
Super Group Semiconductor Co. and Niko Niko | Date: 2014-12-18

A package structure and a packaging method of wafer level chip scale package are provided. The packaging method includes: providing a carrier, and disposing a plurality of chips on the carrier; forming a plurality of adhesive layers on a surface of the corresponding chips; covering a conductive cover plate, bonding the conductive cover plate with the chips through the adhesive layers, and dividing out a plurality of packaging spaces by the conductive cover plate for disposing the chips respectively; and providing an insulation material to fill the packaging spaces through via holes on the conductive cover plate to form a first insulation structure; finally, removing the carrier.


Patent
Niko Niko | Date: 2012-09-10

A multiphase DC-to-DC converter is disclosed herein, which includes at least one DC-to-DC converting module. Each DC-to-DC converting module at least includes a first output inductor, a second output inductor and a current detector. The current detector is configured for detecting currents pass through the first output inductor and second output inductor. The current detector includes a first resistance, a second resistance, a first capacitor, a second capacitor, and a third resistance. The third resistance is directly or indirectly coupled between the first capacitor and a load circuit, and directly or indirectly coupled between the second capacitor and the load circuit, such that when the first capacitor is charged, a portion of the current charging the first capacitor passes through the second capacitor.


Patent
Niko Niko and Super Group Semiconductor Co. | Date: 2015-07-03

A fan-out wafer level chip package structure and the manufacturing method thereof are provided. The method includes the steps of providing a supporting plate having a removable tape formed on the supporting plate, placing a plurality of chips on the removable tape, applying an adhesive layer on a back surface of each of the chips, providing a conductive cover for covering all chips and isolating the chips from each other by a plurality of partitions, injecting a molding compound into an inside of the conductive cover and curing the molding compound for forming an encapsulation, separating the encapsulation from the supporting plate, forming a connection layer on an active surface of each of the chips to establish electrical connections, and performing a cutting process to divide the encapsulation into a plurality of the package structures.

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