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Seoul, South Korea

Kim J.,University of California at Los Angeles | Choi H.,Nexuschip Co. | Yoon S.,Nexuschip Co. | Bang T.,Nexuschip Co. | And 3 more authors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems | Year: 2011

A 3-D graphics SoC, with a multi-layer advanced microcontroller bus architecture (AMBA) system, full pipelined hardware 3-D graphics accelerator, and clock/power management is proposed as a 49-mm2 die for 180-nm CMOS technology. This system-on-chip (SoC) minimizes power consumption with a clock/power management unit according to its operation mode and applications. The 3-D graphics accelerator has a full pipelined architecture which improves full 3-D graphics performance to 8M polygons/s and consumes 108 mW at 100 MHz and 1.8 V. The LCD bypass mode and power-down mode consume 4.32 mW and 180 uW, respectively. The 3-D graphics accelerator also supports stereoscopic 3-D function with an alternative left-right drawing method and achieves a 59% improvement in 3DG performance compared to previous work. © 2010 IEEE. Source

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