Zhang B.,National Digital Switching System Engineering Technical Researching Center |
Wang B.,NDSC |
Journal of Convergence Information Technology | Year: 2012
Network is rigid and close in traditional technology framework which is not meeting scale application requirement of intending abundant different business. So flexible network technology framework facing on service providing is proposed which changes traditional close coupling connection of client business, network service and network foundation facilities to loose coupling connection. Quality of Service(QoS) can be guaranteed by constituting Reconfigurable Service Carrying Network (RSCN) based on network resource slicing. This paper realizes crossbar switching resource slicing by selecting part crossbars closed on new technology framework. Slicing Domain-Maximum Urgency First(SD-MUF) scheduling algorithm is proposed and deduced based on Combined Input-Crosspoint Queued(CICQ). Then it compares SD-MUF-RR with previous proposed MUF-RR and other -RR scheduling algorithms about time delay by 8x8 crossbar switching fabric divided into three slicing domains in Switching Performance Evaluation System (SPES). The result indicates that average delay of SD-MUF-RR scheduling algorithm is less than others in despite of Bernoulli uniform business source or diagonal business source.
Liu Q.,NDSC |
Zhou D.,NDSC |
Wang S.,NDSC |
Electronics Letters | Year: 2016
A non-degenerate dual-mode resonator derived from circular substrate integrated waveguide is proposed, and two pseudoelliptic bandpass filters with non-resonant mode based on the dual-mode resonators are presented. Two resonant modes (higher order modes) are employed to degenerate a passband, while a non-resonant mode (fundamental mode) is designed to provide a direct input-to-output coupling. Owning to an additional path provided by non-resonant mode, the filters have good selectivity and very compact size. The presented simulation and measurement results are in good agreement. © 2016 The Institution of Engineering and Technology.
He H.,NDSC |
Jiang L.,NDSC |
Chen H.,NDSC |
CSAE 2012 - Proceedings, 2012 IEEE International Conference on Computer Science and Automation Engineering | Year: 2012
X86 emulation is an effectively method to solve the problem of software compatible between X86 and RISC processors, such as ARM, PowerPC, Alpha and so on. Dynamic Binary Translation (DBT) in X86 emulation translates the X86 binary codes to RISC binary code dynamically so that the software based on X86 platform could execute undifferentiated on RISC platform. However, the DBT based on software is one of the performance bottlenecks nowadays. In this case, this paper discusses a new method for DBT with hardware/software co-design. A hardware unit is designed to accelerate the DBT system, including Instruction Decoder, RISC Code Table, Translation Cache and Cache Query Unit. Instruction Decoder analyses the meaning of X86 binary codes and then looks up RISC Code Table to obtain the corresponding RISC binary codes. Translation Cache stores the recently translated RISC binary codes to reduce the repeated instruction translation. Cache Query Unit is used to determine whether cache hit or not. Finally, we achieve the hardware unit using Verilog HDL. Experiment showed that the co-design DBT system could work accurately. © 2012 IEEE.
Chen H.-F.,NDSC |
Jiang L.-H.,NDSC |
Dong W.-Y.,NDSC |
Proceedings - 2011 International Conference on Intelligence Science and Information Engineering, ISIE 2011 | Year: 2011
System emulation provides a new solution for software migrating on heterogeneous platform. As one of the important components of system emulation, memory emulation directly affects the performance of system. This paper presents a universal emulation model of IA-32 memory management with Software MMU, virtual TLB and virtual MMIO. and an IA-32 memory management emulator prototype is implemented successfully on the Alpha platform which achieves about 10% of the host machine's performance presently. Compared to Bochs, the performance of our emulator has increased by about 17 percent. © 2011 IEEE.
Jiang L.,NDSC |
Chen H.,NDSC |
Lu J.,NDSC |
Advances in Intelligent and Soft Computing | Year: 2011
IA-32 emulation is a good solution to software compatibility for new computer architecture. However, the address translation from guest machine to host machine is one of the most costly process in IA-32 emulation. To reduce the translation overhead, this paper presented a Pre-TLB with a prefetching window which could predict the memory access of guest machine. The prefetching window slides with the current address which causes a Pre-TLB miss. All entries in the prefetching window are translated at the same time so that several times of memory access can be reduced. Experiments showed that Pre-TLB had a good performance both on hit rate and time cost. For the program with conspicuous locality property, Pre-TLB could only obtain an improvement of 2%. However, for the program with little locality property, the hit rate improved by 9%, and the time cost reduced by 20%. © 2011 Springer-Verlag Berlin Heidelberg.