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NBE Technologies, LLC

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Kim W.,Virginia Polytechnic Institute and State University | Luo S.,NBE Technologies, LLC | Lu G.-Q.,Virginia Polytechnic Institute and State University | Ngo K.D.T.,Virginia Polytechnic Institute and State University
Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC | Year: 2013

A planar power module was developed, and a gate-driver circuit with an over-current protection was planned to integrate into the module. After reviewing several current-sensing methods, the giant-magneto-resistive (GMR) sensor was chosen as a current-sensing method. However, there were several factors that hindered accurate measurement. The high junction temperature of the power dice gave high influence to the operating temperature of the GMR sensor, and the magnetic-flux distribution seen by the GMR sensor was also non-uniform due to skin effect. The temperature response of the GMR sensor was analyzed by experiments, and the GMR sensor showed about 3.45% errors when it sensed 80 Adc and the operating temperature changed by 60°C. To further improve the measurement capability over wide range of operating temperature, an active temperature-compensation method is described. The optimal position of the GMR sensor was found based on FEA simulation as the midpoint of two current paths. At that location, the GMR sensor could consistently sense both current excitations. A test module was fabricated, and preliminary measurement result showed excessive noise that had to be filtered out for accurate measurement. A signal-conditioning circuit was designed using an instrumentation amplifier, and the current measurement between the GMR sensor and a high-bandwidth current probe showed consistent result. The current sensor with signal-conditioning circuit was integrated into the gate-driver circuit, and the concept was verified by experiments. © 2013 IEEE.


Lei T.G.,Virginia Polytechnic Institute and State University | Calata J.N.,Virginia Polytechnic Institute and State University | Lu G.-Q.,Virginia Polytechnic Institute and State University | Chen X.,Tianjin University | Luo S.,NBE Technologies, LLC
IEEE Transactions on Components and Packaging Technologies | Year: 2010

A low-temperature sintering technique enabled by a nanoscale silver paste has been developed for attaching large-area (>100 mm2) semiconductor chips. This development addresses the need of power device or module manufacturers who face the challenge of replacing lead-based or lead-free solders for high-temperature applications. The solder-reflow technique for attaching large chips in power electronics poses serious concern on reliability at higher junction temperatures above 125°C. Unlike the soldering process that relies on melting and solidification of solder alloys, the low-temperature sintering technique forms the joints by solid-state atomic diffusion at processing temperatures below 275°C, with the sintered joints having the melting temperature of silver at 961°C. Recently, we showed that a nanoscale silver paste could be used to bond small chips at temperatures similar to soldering temperatures without any externally applied pressure. In this paper, we extend the use of the nanomaterial to attach large chips by introducing a low pressure up to 5 MPa during the densification stage. Attachment of large chips to substrates with silver, gold, and copper metallization is demonstrated. Analyses of the sintered joints by scanning acoustic imaging and electron microscopy showed that the attachment layer had a uniform microstructure with micrometer-sized porosity with the potential for high reliability under high-temperature applications. © 2006 IEEE.


Zheng H.,Virginia Polytechnic Institute and State University | Berry D.,Virginia Polytechnic Institute and State University | Calata J.N.,Virginia Polytechnic Institute and State University | Ngo K.D.T.,Virginia Polytechnic Institute and State University | And 2 more authors.
IEEE Transactions on Components, Packaging and Manufacturing Technology | Year: 2013

Low-temperature joining technology using nanosilver paste has been widely demonstrated for attaching power chips on silver or gold metallized substrates. In this paper, we investigate the processing conditions of nanosilver paste for bonding large-area chips on a plain copper surface. A double-print, low-pressure-assisted sintering process is developed for attaching the chips on copper. An evaluation criterion used in the process development is the bond strength of mechanical chips that are made of alumina and sintered on direct-bond-copper (DBC) substrates. The bond strength, measured by the die-shear test, is found to be in excess of 40 and 77 MPa at sintering pressures of 3 and 12 MPa, respectively, during sintering. Characterization of the bondline microstructure reveals a void-free sintered joint, the density of which increases, with increasing sintering pressure. Sintering in air causes partial oxidation of the copper surface, but the oxide can be easily removed by dipping in 1% hydrochloric acid solution. To evaluate the impact of the bonding and acid-cleaning process on device characteristics, a large-area insulated-gate-bipolar-transistor (IGBT) chip is bonded to DBC substrate and then wire-bonded for electrical testing. Test results shows that the die-attach process does not alter the IGBT performance. © 2011-2012 IEEE.


Wang T.,Virginia Polytechnic Institute and State University | Wang T.,Tianjin University | Zhao M.,Virginia Polytechnic Institute and State University | Chen X.,Tianjin University | And 3 more authors.
Journal of Electronic Materials | Year: 2012

The drying and densification behavior of a nanosilver paste was studied by shrinkage and weight-loss measurements to provide fundamental understanding on the sintering behavior of the nanomaterial for packaging power devices and modules. The measured shrinkage behavior was found to be in good agreement with the weight-loss behavior of the paste as measured by thermogravitational analysis, and the comparison offered direct evidence of ∼10% shrinkage contributed by late-stage densification of silver nanoparticles (NPs). It was found that sintered silver joints could be achieved without cracks or delamination under a ramp-soak temperature profile for bonding small-area chips, e.g., 3 mm × 3 mm or smaller. However, for bonding large-area chips, e.g., 5 mm × 5 mm or larger, rapid evaporation of the entrapped organic species caused the chips to delaminate, leading to large longitudinal cracks at the joint interface. Finally, examination of the microstructure evolution of the silver die-attach material revealed that binder molecules inhibited necking of the silver NPs and delayed densification during the sintering process of the nanosilver paste. © 2012 TMS.


Mei Y.,Tianjin University | Mei Y.,Virginia Polytechnic Institute and State University | Lu G.-Q.,Virginia Polytechnic Institute and State University | Chen X.,Tianjin University | And 2 more authors.
IEEE Transactions on Device and Materials Reliability | Year: 2011

The low-temperature joining of semiconductor chips by sintering of silver paste is emerging as an alternative lead-free solution for power electronics devices and modules working in a high-temperature environment. A promising die-attachment material that would enable the rapid implementation of the sintering process is nanoscale silver paste, which can be sintered at temperatures below 300 °C without an external pressure. In this paper, we report our findings on the silver migration in sintered nanosilver electrode-pair patterns on an alumina substrate. The electrode pairs were biased at an electric field ranging from 10 to 100 V/mm and at a temperature between 250 C° and 400 °C in dry air. The leakage currents across the electrodes were measured as the silver patterns were tested in an oven. Silver dendrites formed across the electrode gap were observed under an optical microscope and analyzed using scanning electron microscopy and energy dispersive spectroscopy (EDS). The silver migration was found in the samples tested at 400 °C, 350 °C 300 °C, and 250 C°. The measurements on the leakage current versus time were characterized by an initial incubation period, called lifetime, followed by a sharp rise as the silver dendrites were shorting the electrodes. A simple phenomenological model was derived to account for the observed dependence of lifetime on the electric field and temperature. The EDS mappings revealed the significant presence of oxygen on the positive electrode but the complete absence on the negative electrode. A mechanism involving the oxidation of silver and the dissociation of silver oxide at the anode was suggested. We suggest that the migration of a sintered nanosilver die attachment can be prevented in high-temperature applications through packaging or encapsulation to reduce the partial pressure of oxygen. © 2011 IEEE.


Grant
Agency: National Science Foundation | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 150.00K | Year: 2013

This Small Business Innovative Research (SBIR) Phase I project is aimed at demonstrating the feasibility of an electronic packaging technology for manufacturing power electronics modules that are critical for electrical energy processing in a wide range of systems, such as hybrid or electric vehicles, renewable energy generators, and the power grid. Recent advances in power semiconductor devices and substrate technology require packaging schemes which optimize the performance of each component for further increases in reliability, density, and high-temperature performance. The best route for meeting this need is to explore three dimensional package architectures which have previously been a barrier for manufacturing using solder techniques. This project will build on the commercialization success of a nanomaterial technology for device interconnection, to develop and implement an innovative three dimensional package architecture which can be force cooled equally well from both sides. The nanomaterial, which already boasts significant increases in thermal and electrical conductivity, is known to provide high reliability and high temperature joints for device interconnection. In addition, processing requirements can be tailored to significantly simplify fabrication of architectures which are difficult to create using existing solder and epoxy connection schemes. Utilizing the processing benefits of the nanomaterial die attachment, the specific technical objectives are: (1) development of a manufacturable process with the nanomaterial for fabricating the planar power modules; (2) testing of the modules under applied continuous current; and (3) evaluation of the module reliability under temperature/power cycling tests and (4) characterization of failure mechanisms. The double-side cooled planar power module technology enabled by the nanomaterial would lead to a highly competitive product in the market place. The broader impact/commercial potential of this project would strengthen United States? manufacturing base in the field of power electronics. Power electronics modules are the central processing units for electrical energy conversion and are crucial to the nation?s economy and security. Energy applications, specifically those that provide independence from petroleum, require more efficient conversion of electrical power, and demand for reliability and sustainability of the nation?s power infrastructure requires an increasingly greater number of electrical conversions. Currently, the market of power electronics modules is dominated by products made in Europe and Asia. Successful commercialization of the technology developed in this project would usher in a competitive US manufacturer of power modules to the growing power electronics market. The success would further strengthen commercialization effort of the nanomaterial product developed under a NSF STTR program and directly translate to economic growth for Southwest Virginia. Success of this program would also serve as a good educational and business model for transferring fundamental knowledge developed under NSF?s support into the commercial world. It would present students an ideal case study to experience technological and economical impacts of their research activities.


Grant
Agency: Department of Energy | Branch: | Program: SBIR | Phase: Phase II | Award Amount: 1.00M | Year: 2010

This proposal addresses the Department of Energy


Grant
Agency: NSF | Branch: Standard Grant | Program: | Phase: | Award Amount: 150.00K | Year: 2013

This Small Business Innovative Research (SBIR) Phase I project is aimed at demonstrating the feasibility of an electronic packaging technology for manufacturing power electronics modules that are critical for electrical energy processing in a wide range of systems, such as hybrid or electric vehicles, renewable energy generators, and the power grid. Recent advances in power semiconductor devices and substrate technology require packaging schemes which optimize the performance of each component for further increases in reliability, density, and high-temperature performance. The best route for meeting this need is to explore three dimensional package architectures which have previously been a barrier for manufacturing using solder techniques. This project will build on the commercialization success of a nanomaterial technology for device interconnection, to develop and implement an innovative three dimensional package architecture which can be force cooled equally well from both sides. The nanomaterial, which already boasts significant increases in thermal and electrical conductivity, is known to provide high reliability and high temperature joints for device interconnection. In addition, processing requirements can be tailored to significantly simplify fabrication of architectures which are difficult to create using existing solder and epoxy connection schemes. Utilizing the processing benefits of the nanomaterial die attachment, the specific technical objectives are: (1) development of a manufacturable process with the nanomaterial for fabricating the planar power modules; (2) testing of the modules under applied continuous current; and (3) evaluation of the module reliability under temperature/power cycling tests and (4) characterization of failure mechanisms. The double-side cooled planar power module technology enabled by the nanomaterial would lead to a highly competitive product in the market place.

The broader impact/commercial potential of this project would strengthen United States? manufacturing base in the field of power electronics. Power electronics modules are the central processing units for electrical energy conversion and are crucial to the nation?s economy and security. Energy applications, specifically those that provide independence from petroleum, require more efficient conversion of electrical power, and demand for reliability and sustainability of the nation?s power infrastructure requires an increasingly greater number of electrical conversions. Currently, the market of power electronics modules is dominated by products made in Europe and Asia. Successful commercialization of the technology developed in this project would usher in a competitive US manufacturer of power modules to the growing power electronics market. The success would further strengthen commercialization effort of the nanomaterial product developed under a NSF STTR program and directly translate to economic growth for Southwest Virginia. Success of this program would also serve as a good educational and business model for transferring fundamental knowledge developed under NSF?s support into the commercial world. It would present students an ideal case study to experience technological and economical impacts of their research activities.


Mei Y.,Virginia Polytechnic Institute and State University | Mei Y.,Tianjin University | Lu G.-Q.,Virginia Polytechnic Institute and State University | Chen X.,Tianjin University | And 2 more authors.
IEEE Transactions on Device and Materials Reliability | Year: 2011

The low-temperature joining technique of silver sintering is being actively pursued in the power electronics industry as a lead-free die-attach solution for packaging power devices and modules. However, one of the concerns of this technique is the migration of silver at a high temperature. Recently, we have reported our findings of the migration of a low-temperature sintered nanosilver in dry air at a temperature over 250 °C. In this paper, we report our results of the effect of oxygen partial pressure on the migration kinetics of the sintered nanosilver at 400 °C under an electrical field strength of 50 V/mm. The range of the oxygen partial pressure tested was between < 0.01 and 0.40 atm. The silver migration kinetics were monitored by measuring the leakage current across a metal-finger pattern, which allowed the determination of the lifetime, or the onset time for significant leakage current developed across the two electrodes. With decreasing oxygen partial pressure, the lifetime increases exponentially. Our results suggest that the concern for silver migration in a high-temperature application of sintered silver die attach can be effectively remedied through packaging to keep oxygen away from the silver joints. © 2011 IEEE.


Mei Y.,Tianjin University | Lu G.-Q.,Virginia Polytechnic Institute and State University | Chen X.,Tianjin University | Gang C.,Tianjin University | And 2 more authors.
Journal of Electronic Materials | Year: 2011

For many years, direct bonded copper (DBC) substrates have proved to be an excellent solution for electrical isolation and thermal management of high-power semiconductor modules. However, in this study we detected a copper residue on the surface of DBC alumina, presumably a result of pattern etching even in industry. As is known, growth of metal dendrites could be observed with the assistance of electric field, temperature, and humidity. Metal dendrites normally grow from the cathode to anode. Silver and copper are two kinds of metals susceptible to migration. In this work, copper dendrites could be formed at 400°C and 50 V/mm between conductors. These dendrites may impact the reliability of DBC in power electronic applications. Therefore, the formation of copper residue is an interesting phenomenon for etched DBC and warrants further attention in the future. © 2011 TMS.

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