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Liu L.,National Laboratory of Analog ICs | Liu L.,University of Electronic Science and Technology of China | Gao Y.,Sichuan Institute of Solid State Circuits | Li R.,National Laboratory of Analog ICs | And 3 more authors.
IET Conference Publications | Year: 2010

The challenges for next generation wireless systems will increase even further, when designs must be targeted to multi-standard and re-configurability requirements. The ideal software-defined radio architecture is introduced and the practical limitations of current technology are highlighted, which make this architecture currently unrealizable. A structure of RF SOC is presented. To simulate the bit-error-rate (BER) and eye diagrams of a complete receiver link, we combine MATLAB/Simulink modeling and simulation capabilities with the analog simulation capability of AMS. This co-simulation process allows users to easily perform system level test on the analog circuit being designed.


Liu L.,National Laboratory of Analog ICs | Liu L.,University of Electronic Science and Technology of China | Gao Y.,Sichuan Institute of Solid State Circuits | Li R.,National Laboratory of Analog ICs | And 3 more authors.
IET Conference Publications | Year: 2010

Increasing numbers of high-density and high-speed mixed circuits has been integrated on a single chip, while the devices are becoming more sensitive to the simultanous switching noise. In this paper,a chip-package co-design method is presented for co-design of chip and package. Based on the analysis of simulation result of package and chip, a special circuit which is composed of resistors and capacitor is designed on chip to decrease the affect of simultaneous switch noise. The simulation shows an excellent agreement with measurement within a 1% margin.


Yang Y.,Sichuan Institute of Solid State Circuits | Yang Y.,National Laboratory of Analog ICs | Tang Z.,Sichuan Institute of Solid State Circuits | Zhang Z.,Sichuan Institute of Solid State Circuits | And 7 more authors.
Journal of Semiconductors | Year: 2011

A novel structure of a VDMOS in reducing on-resistance is proposed. With this structure, the specific on-resistance value of the VDMOS is reduced by 22% of that of the traditional VDMOS structure as the breakdown voltage maintained the same value in theory, and there is only one additional mask in processing the new structure VDMOS, which is easily fabricated. With the TCAD tool, one 200 V N-channel VDMOS with the new structure is analyzed, and simulated results show that a specific on-resistance value will reduce by 23%, and the value by 33% will be realized when the device is fabricated in three epitaxies and four buried layers. The novel structure can be widely used in the strip-gate VDMOS area.


Kaizhou T.,National Laboratory of Analog ICs | Zhaohuan T.,National Laboratory of Analog ICs | Jun L.,Sichuan Institute of Solid State Circuits | Shendong H.,National Laboratory of Analog ICs | And 3 more authors.
IEEE Region 10 Annual International Conference, Proceedings/TENCON | Year: 2013

A novel low on-resistance 600V structure with Split P-Buried Floating Layer(SBFL) and doping trench is proposed and demonstrated by simulation. This novel structure can overcome big reverse leakage current problem of conventional SBFL, and keep its low on-resistance advantage. Its specific on-resistance is 43% less than ideal parallel-plane junction stucture at 600V blocking voltage, from 73.3 mO.cm2 to 41.7 mO.cm2. © 2013 IEEE.


Sheng X.,Sichuan Institute of Solid State Circuits | Peng K.,Sichuan Institute of Solid State Circuits | Zhang Z.,Sichuan Institute of Solid State Circuits | Zhang Z.,National Laboratory of Analog ICs | And 3 more authors.
Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014 | Year: 2014

The research of failure analysis for integrated circuits can improve the reliability. Based on one failed circuit, do the analysis which including eletrical parameter test, chip surface check, schematic diagram and layout analysis, and find the failure reason, then use simulation to verify the analized conclusion. Finally, throw out some effective ways to avoid this kind of failure that might happen again, which is helpful for improving the reliability of integrated circuits. © 2014 IEEE.


Zhang R.,National Laboratory of Analog ICs | Yu J.,National Laboratory of Analog ICs | Zhang Z.,Sichuan Institute of Solid State Circuits | Wang Y.,National Laboratory of Analog ICs | And 2 more authors.
Proceedings - 2010 International Conference on Anti-Counterfeiting, Security and Identification, 2010 ASID | Year: 2010

In this paper, a digital calibration algorithm for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology is presented. The spice simulation result shows the digital foreground calibration algorithm can efficiently improve the linearity of the ADC. © 2010 IEEE.


Yu J.,National Laboratory of Analog ICs | Yu J.,12th Institute of CETC | Yu J.,Changsha University | Zhang R.,National Laboratory of Analog ICs | And 5 more authors.
ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings | Year: 2010

A digital calibration implementation for track-and-hold offset in a high-speed timing-interleaved folding and interpolating analog-to-digital converter is proposed in this paper. The spice simulation and measured results both show that the digital calibration technique can efficiently cancel the T/H offset and improve the linearity of the ADC. ©2010 IEEE.


Yu J.,National Laboratory of Analog ICs | Yu J.,12th Institute of CETC | Yu J.,Changsha University | Zhang R.,National Laboratory of Analog ICs | And 6 more authors.
Journal of Semiconductors | Year: 2011

A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.


Gao Y.,National Laboratory of Analog ICs | Liu L.,National Laboratory of Analog ICs | Liu L.,University of Electronic Science and Technology of China | Chen L.,National Laboratory of Analog ICs | And 2 more authors.
2010 Academic Symposium on Optoelectronics and Microelectronics Technology and 10th Chinese-Russian Symposium on Laser Physics and Laser Technology, RCSLPLT/ASOT 2010 | Year: 2010

A chip-package co-design method is presented for high frequency mixed SoC. Based on the analysis of simulation result of package and chip, a RC circuit which is composed of resistor and capacitor is designed on chip to suppress the affect of Simultaneous Switch Noise(SSN). Consequently, chip-package co-simulation achieves a good agreement with measurement as the co-design method is used to predict the performance of mixed SoC. © 2010 IEEE.


Cui W.,State Key Laboratory of Electronic Thin Films and Integrated Devices | Cui W.,National Laboratory of Analog ICs | Xu S.,National Laboratory of Analog ICs | Li P.,State Key Laboratory of Electronic Thin Films and Integrated Devices | And 2 more authors.
Advanced Materials Research | Year: 2011

In this paper, we propose a novel material- amorphous silicon germanium(a-SiGe). The a-SiGe film was formed by PECVD at a low temperature and a low frequency. By adjusting the fraction x of Ge in Si1-xGex, optimal SiGe bandgap was achieved. We used amorphous silicon germanium alloy as MOSFET source/drain. The parameter of MOSFET shows that, as the fraction increases, the drain-to-source breakdown voltage increases. With reduction of the minority carrier inject ratio, the current gain β of parasitic BJT in MOSFET was reduced greatly, which eliminates the limit of the breakdown voltage of the device. © (2011) Trans Tech Publications, Switzerland.

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