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Sheng X.,Sichuan Institute of Solid State Circuits | Peng K.,Sichuan Institute of Solid State Circuits | Zhang Z.,Sichuan Institute of Solid State Circuits | Zhang Z.,National Laboratory of Analog ICs | And 3 more authors.
Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014 | Year: 2014

The research of failure analysis for integrated circuits can improve the reliability. Based on one failed circuit, do the analysis which including eletrical parameter test, chip surface check, schematic diagram and layout analysis, and find the failure reason, then use simulation to verify the analized conclusion. Finally, throw out some effective ways to avoid this kind of failure that might happen again, which is helpful for improving the reliability of integrated circuits. © 2014 IEEE. Source


Kaizhou T.,National Laboratory of Analog ICs | Zhaohuan T.,National Laboratory of Analog ICs | Jun L.,Sichuan Institute of Solid State Circuits | Shendong H.,National Laboratory of Analog ICs | And 3 more authors.
IEEE Region 10 Annual International Conference, Proceedings/TENCON | Year: 2013

A novel low on-resistance 600V structure with Split P-Buried Floating Layer(SBFL) and doping trench is proposed and demonstrated by simulation. This novel structure can overcome big reverse leakage current problem of conventional SBFL, and keep its low on-resistance advantage. Its specific on-resistance is 43% less than ideal parallel-plane junction stucture at 600V blocking voltage, from 73.3 mO.cm2 to 41.7 mO.cm2. © 2013 IEEE. Source


Liu L.,National Laboratory of Analog ICs | Liu L.,University of Electronic Science and Technology of China | Gao Y.,Sichuan Institute of Solid State Circuits | Li R.,National Laboratory of Analog ICs | And 3 more authors.
IET Conference Publications | Year: 2010

The challenges for next generation wireless systems will increase even further, when designs must be targeted to multi-standard and re-configurability requirements. The ideal software-defined radio architecture is introduced and the practical limitations of current technology are highlighted, which make this architecture currently unrealizable. A structure of RF SOC is presented. To simulate the bit-error-rate (BER) and eye diagrams of a complete receiver link, we combine MATLAB/Simulink modeling and simulation capabilities with the analog simulation capability of AMS. This co-simulation process allows users to easily perform system level test on the analog circuit being designed. Source


Liu L.,National Laboratory of Analog ICs | Liu L.,University of Electronic Science and Technology of China | Gao Y.,Sichuan Institute of Solid State Circuits | Li R.,National Laboratory of Analog ICs | And 3 more authors.
IET Conference Publications | Year: 2010

Increasing numbers of high-density and high-speed mixed circuits has been integrated on a single chip, while the devices are becoming more sensitive to the simultanous switching noise. In this paper,a chip-package co-design method is presented for co-design of chip and package. Based on the analysis of simulation result of package and chip, a special circuit which is composed of resistors and capacitor is designed on chip to decrease the affect of simultaneous switch noise. The simulation shows an excellent agreement with measurement within a 1% margin. Source


Yu J.,National Laboratory of Analog ICs | Yu J.,12th Institute of CETC | Yu J.,Changsha University | Zhang R.,National Laboratory of Analog ICs | And 5 more authors.
ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings | Year: 2010

A digital calibration implementation for track-and-hold offset in a high-speed timing-interleaved folding and interpolating analog-to-digital converter is proposed in this paper. The spice simulation and measured results both show that the digital calibration technique can efficiently cancel the T/H offset and improve the linearity of the ADC. ©2010 IEEE. Source

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