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Ming Z.,Harbin Institute of Technology | Ming Z.,National Key Laboratory Of Science And Technology On Reliability Physics And Applic Technology Of Electrical Component | Yi X.L.,National Key Laboratory Of Science And Technology On Reliability Physics And Applic Technology Of Electrical Component | Chang L.,National Key Laboratory Of Science And Technology On Reliability Physics And Applic Technology Of Electrical Component | Wei Z.J.,Dalian University of Technology
IEEE Transactions on Nuclear Science | Year: 2011

As technology scales, more and more memory cells can be placed in a die. Therefore, the probability that a single event induces multiple bit upsets (MBUs) in adjacent memory cells gets greater. Generally, multibit error correction codes (MECCs) are effective approaches to mitigate MBUs in memories. In order to evaluate the robustness of protected memories, reliability models have been widely studied nowadays. Instead of irradiation experiments, the models can be used to quickly evaluate the reliability of memories in the early design. To build an accurate model, some situations should be considered. Firstly, when MBUs are presented in memories, the errors induced by several events may overlap each other, which is more frequent than single event upset (SEU) case. Furthermore, radiation experiments show that the probability of MBUs strongly depends on angles of the radiation event. However, reliability models which consider the overlap of multiple bit errors and angles of radiation event have not been proposed in the present literature. In this paper, a more accurate model of memories with MECCs is presented. Both the overlap of multiple bit errors and angles of event are considered in the model, which produces a more precise analysis in the calculation of mean time to failure (MTTF) for memory systems under MBUs. In addition, memories with scrubbing and nonscrubbing are analyzed in the proposed model. Finally, we evaluate the reliability of memories under MBUs in Matlab. The simulation results verify the validity of the proposed model. © 2011 IEEE. Source


Liu L.,Xidian University | Liu L.,Key Laboratory of Wide Band Gap Semiconductor Materials and Devices | Zou J.,Xidian University | En Y.,National Key Laboratory Of Science And Technology On Reliability Physics And Applic Technology Of Electrical Component | And 6 more authors.
Journal of Semiconductors | Year: 2014

As the front-end preamplifiers in optical receivers, transimpedance amplifiers (TIAs) are commonly required to have a high gain and low input noise to amplify the weak and susceptible input signal. At the same time, the TIAs should possess a wide dynamic range (DR) to prevent the circuit from becoming saturated by high input currents. Based on the above, this paper presents a CMOS transimpedance amplifier with high gain and a wide DR for 2.5 Gbit/s communications. The TIA proposed consists of a three-stage cascade pull push inverter, an automatic gain control circuit, and a shunt transistor controlled by the resistive divider. The inductive-series peaking technique is used to further extend the bandwidth. The TIA proposed displays a maximum transimpedance gain of 88.3 dBΩ with the -3 dB bandwidth of 1.8 GHz, exhibits an input current dynamic range from 100 nA to 10 mA. The output voltage noise is less than 48.23 nV/Hz within the -3 dB bandwidth. The circuit is fabricated using an SMIC 0.18 μm 1P6M RFCMOS process and dissipates a dc power of 9.4 mW with 1.8 V supply voltage. © 2014 Chinese Institute of Electronics. Source


Zhu M.,Harbin Institute of Technology | Xiao L.Y.,Harbin Institute of Technology | Song L.L.,Harbin Institute of Technology | Zhang Y.J.,Harbin Institute of Technology | Luo H.W.,National Key Laboratory Of Science And Technology On Reliability Physics And Applic Technology Of Electrical Component
Microelectronics Journal | Year: 2011

Nowadays, multibit error correction codes (MECCs) are effective approaches to mitigate multiple bit upsets (MBUs) in memories. As technology scales, combinational circuits have become more susceptible to radiation induced single event transient (SET). Therefore, transient faults in encoding and decoding circuits are more frequent than before. Firstly, this paper proposes a new MECC, which is called Mix code, to mitigate MBUs in fault-secure memories. Considering the structure characteristic of MECC, Euclidean Geometry Low Density Parity Check (EG-LDPC) codes and Hamming codes are combined in the proposed Mix codes to protect memories against MBUs with low redundancy overheads. Then, the fault-secure scheme is presented, which can tolerate transient faults in both the storage cell and the encoding and decoding circuits. The proposed fault-secure scheme has remarkably lower redundancy overheads than the existing fault-secure schemes. Furthermore, the proposed scheme is suitable for ordinary accessed data width (e.g., 2n bits) between system bus and memory. Finally, the proposed scheme has been implemented in Verilog and validated through a wide set of simulations. The experiment results reveal that the proposed scheme can effectively mitigate multiple errors in whole memory systems. They can not only reduce the redundancy overheads of the storage array but also improve the performance of MECC circuits in fault-secure memory systems. © 2011 Elsevier Ltd. All rights reserved. Source


Ming Z.,Harbin Institute of Technology | Yi X.L.,Harbin Institute of Technology | Wei L.H.,National Key Laboratory Of Science And Technology On Reliability Physics And Applic Technology Of Electrical Component
2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011 | Year: 2011

Nowadays, multiple bit upsets (MBUs) have been widely investigated in memories. Conventional single error correction and double error detection (SEC-DED) codes are capable of correcting one error and detecting all possible double errors. However, they may not provide adequate protection against MBUs. This paper proposes new single-error-correction, double-error-detection double-adjacent-error-correction (SEC-DED-DAEC) codes to mitigate radiation or noise source induced MBUs in memories. The proposed SEC-DED-DAEC codes are obtained from conventional SEC-DED codes according to the mathematics model established in this paper. They can detect and correct all adjacent double bit errors and assure a lower miscorrection probability for non-adjacent double bit errors compared with other SEC-DED-DAEC codes. Furthermore, the redundancy bits of the proposed scheme are the same as those of conventional SEC-DED codes. This means that the increase of correct-capability do not cause additional hardware overhead for the memory system. Finally, the experiment results reveal that the proposed scheme reduces the miscorrection probability of non-adjacent double bit errors by 12% compared to the best known SEC-DED-DAEC codes. Moreover, compared to the well known BCH codes, the proposed scheme reduces 40% hardware redundancy and keeps an acceptable reliability. © 2011 IEEE. Source


Yi X.L.,Harbin Institute of Technology | Ming Z.,Harbin Institute of Technology | Jing Z.Y.,Harbin Institute of Technology | Wei L.H.,National Key Laboratory Of Science And Technology On Reliability Physics And Applic Technology Of Electrical Component
2011 Academic International Symposium on Optoelectronics and Microelectronics Technology, AISOMT 2011 | Year: 2011

As the feature sizes of integrated circuits decreasing, single event transient (SET) in combinational circuits can not been ignored any longer. In this paper, a novel fault-secure scheme for memory has been proposed by studying the structural features of Euclidean Geometry-Low Density Parity Check (EG-LDPC) codes. The proposed fault-secure scheme can tolerate transient faults both in the storage cell and in the encoder and decoder, using the parallel majority decoding and the feedback loop structure. In order to improve the decoding speed, an algorithm is presented, which can reduce the majority decoding of EG-LDPC codes into two steps. Furthermore, the proposed scheme can suit ordinary data width (e.g., 2 n bits) in memory. Finally, the correcting capability and the reliability of the proposed scheme are analyzed. The experiment results reveal that the Mean Time to Failure (MTTF) of the proposed scheme is 419%, 104% and 118% compared with that of Hamming code, Matrix code and Reed-Muller code, respectively. © 2011 IEEE. Source

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