National High Performance Shanghai Design Center

Shanghai, China

National High Performance Shanghai Design Center

Shanghai, China
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Yang W.,Naval Academy of Armament | Ban D.-S.,National High Performance Shanghai Design Center | Guan D.-L.,Naval Academy of Armament | Ye X.-Q.,Naval Academy of Armament | Dou W.-H.,National University of Defense Technology
Jisuanji Xuebao/Chinese Journal of Computers | Year: 2012

Cooperative sensing technology can greatly improve the spectrum utilization in cognitive radio networks. However, with the formation of cooperative sensing coalition, it inevitably introduces extra cost. All the nodes within a coalition expect to achieve a higher throughput with less extra energy cost. In this paper, we address the multi-objective non-linear programming problem for cooperative sensing. Based on coalition game theory, we construct a non-transferable utility coalition formation game for the problem. In the design of its payoff function, we assign the throughput expectation and the energy cost with different weights, so that these two objectives are jointly considered. After that, we propose a distributed multi-objective coalition formation algorithm DMCF, in which coalition are iterated merged and split according to Pareto order. In addition, we show the convergence of the proposed algorithm and the stability of the final coalition partition. Extensive experiments by simulations demonstrate that, compared with the result delivered by a distributed random coalition formation algorithm DRCF, algorithm DMCF can increase the node's throughput expectation by 7.5%, however decrease the energy cost significantly by 70%, which shows great effectiveness to deal with the proposed multi-objective optimization problem.


Hu X.-D.,National High Performance Shanghai Design Center | Guo Y.,National High Performance Shanghai Design Center | Zhu Y.,National High Performance Shanghai Design Center | Guo X.,National High Performance Shanghai Design Center | Wang P.,National High Performance Shanghai Design Center
Journal of Computer Science and Technology | Year: 2010

Instruction Set Simulator (ISS) is a highly abstracted and executable model of micro architecture. It is widely used in the fields of verification and debugging during the development of microprocessors. However, with the emergence of Chip Multi-Processors, the single-core ISS cannot meet the needs of microprocessor development. In this paper, we introduce our multi-core chip architecture first, after that a general methodology to expand a single-core ISS to a multi-core ISS (MCISS) is proposed. On this basis, a real-time comparison environment is created for multi-core verification, and the problems of multi-core communication and synchronization are addressed gracefully. With the "save and restore" mechanism, the verification procedure and the debugging are speeding up greatly. © 2010 Springer.

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