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Huang J.-F.,National Taiwan University of Science and Technology | Wen J.-Y.,National Communications Commission | Chen W.-C.,National Taiwan University of Science and Technology
Lecture Notes in Electrical Engineering | Year: 2015

A continuous-time low-pass sigma-delta modulator (ΣΔM) with a chain of integrators with weighted capacitive feedforward (CICFF) summation topology is fabricated by TSMC 0.18-μm CMOS process. The summation of feedforward signals is implemented by the weighted capacitors without the necessity of any additional active components. The quantizer uses a 1-bit comparator which may achieve high linearity easily. Under 1.8-V supply voltage, the measured results achieve a dynamic range of 52 dB over a 5-MHz signal bandwidth, a peak SNDR of 53.37 dB, an ENOB of 8.53 bits, an IM3 of –56 dB, and a power dissipation of 11.8 mW. With the pads included, the chip area is 0.35 (0.563 × 0.636) mm2. © Springer International Publishing Switzerland 2015. Source


Huang J.-F.,National Taiwan University of Science and Technology | Yang J.-L.,National Taiwan University of Science and Technology | Chen K.-L.,National Communications Commission
Lecture Notes in Electrical Engineering | Year: 2014

A 5.8-GHz frequency synthesizer is implemented in TSMC 0.18-μm CMOS process. This paper proposes a dynamic current-matching charge pump linearization technique and uses a current-switching differential Colpitts VCO to lower the phase noise and an averaged varactor circuit to increase the linearity of the VCO tuning range. At the supply voltage of 1.8 V, measured results achieve the locked tuning frequency from 5.55 to 5.94 GHz, corresponding to 6.8 % and the phase noise of -105.83 dBc/Hz at 1 MHz offset frequency from 5.8 GHz. The overall power consumption is 21.6 mW. Including pads, the chip area is 0.729 (0.961 × 0.761) mm2. © 2014 Springer International Publishing Switzerland. Source


Huang J.-F.,National Taiwan University of Science and Technology | Wen J.-Y.,National Communications Commission | Jiangn Y.-J.,National Taiwan University of Science and Technology
Lecture Notes in Electrical Engineering | Year: 2014

A 5.8-GHz transceiver front-end applied in dedicated short-range communication (DSRC) systems which is developed in public traffic transportation to improve the safety is fabricated on a chip using TSMC 0.18-μm CMOS process. The proposed prototype includes an asymmetric T/R switch, a current-reused LNA, and a class A power amplifier (PA) on the low-voltage operation in order to minimize the power consumption. Measured results achieve the power gain of 11 dB, the NF of 4.9 dB, the third-order intercept point (IIP3) of -5.4 dBm, and the power consumption of 3.9 mW in the receiving (Rx) mode. On the other hand, the power gain of 12.4 dB, the output 1 dB compression point (OP-1dB) of 11.4 dBm, the PAE of 14.7 % at P-1dB, the IMD3 of -15.8 dBc at 1 dB compression level, the output power of 2.6 dBm with a 50 Ω load, and power consumption of 116.3 mW are obtained in the transmitting (Tx) mode. The overall chip area is 1.5 (1.32 × 1.14) mm 2. This RF CMOS transceiver front-end includes all matching circuits and biasing circuits, and no external components are required. © 2014 Springer International Publishing Switzerland. Source


Wen J.-Y.,National Communications Commission | Chang P.-H.,National Taiwan University of Science and Technology | Huang J.-F.,National Taiwan University of Science and Technology | Lai W.-C.,National Taiwan University of Science and Technology
2015 IEEE International Conference on Signal Processing, Communications and Computing, ICSPCC 2015 | Year: 2015

A 1.8-V 12-bit 5MS/s successive approximation register (SAR) analog-to-digital converter (ADC) implemented in TSMC 0.18-um CMOS process is presented. To reduce DAC switching energy and chip area, a hybrid resistor-capacitor DAC is applied. To save energy, asynchronous control logic to drive the ADC is used. A pre-amplifier based comparator circuit is built to reduce the kickback noise from the dynamic latch designs. With 1.8 V supply voltage and 5.0 MHz sampling rate, measured results achieve -0.55/0.72 LSB (Least Significant Bit) of DNL (differential nonlinearity) and -0.78/0.92 LSB of integral nonlinearity (INL) respectively, and 10.76 bits of an effective number of bits (ENOB) at 1MHz input frequency. The chip area is 0.83 mm2 including pads and the power consumption is 490μW for optical and wireless communications. © 2015 IEEE. Source


Chang F.-C.,National Taiwan Normal University | Chung C.-H.,National Communications Commission | Yu P.-T.,Bureau of Health Promotion | Chao K.-Y.,Bureau of Health Promotion
Health Education Research | Year: 2011

The present study evaluated the impact of Taiwan's graphic cigarette warning labels and smoke-free law on awareness of the health hazards of smoking and thoughts of quitting smoking. National representative samples of 1074 and 1094 people, respectively, were conducted successfully by telephone in July 2008 (pre-law) and March 2009 (post-law). Results reveal that the prevalence of thinking about the health hazards of smoking among smokers increased from 50.6% pre-law to 79.6% post-law, while the prevalence among non-smokers increased from 68.8 to 94.1% during the same period. The prevalence rates of smokers who reported thinking of quitting rose from 30.2% pre-law to 51.7% post-law. Multivariate analyses results indicated that the implementation of graphic warning labels and the smoke-free law significantly increased the odds of awareness about the health hazards of smoking [odds ratio (OR) = 6.39, 95% confidence interval (CI) = 4.84-8.44] and thoughts of quitting smoking (OR = 2.39, 95% CI = 1.48-3.87). In conclusion, the implementation of a smoke-free law in combination with graphic cigarette warning labels has been effective in increasing thoughts about the health hazards of smoking and quitting smoking. © The Author 2010. Source

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