National Center for Advanced Packaging China

Wuxi, China

National Center for Advanced Packaging China

Wuxi, China
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Lin T.,National Center for Advanced Packaging China | Hou F.,National Center for Advanced Packaging China | Hou F.,Chinese Academy of Sciences | Liu H.,National Center for Advanced Packaging China | And 8 more authors.
2016 IEEE CPMT Symposium Japan, ICSJ 2016 | Year: 2016

Nowadays, fan-out package is regarded as one of the latest and most potential technologies due to lower cost, smaller and thinner form factor, better electrical performance, and better thermal performance. Compared with traditional flip chip ball grid array (FCBGA), fan-out technology eliminates many process steps such as substrate, wafer bumping, flip chip reflow, flux cleaning, underfill, etc. However, warpage induced by molding is a critical issue due to the mismatch of the coefficient of thermal expansion (CTE) among the constituent materials, which is needed to be solved for successful subsequent process of the fan-out package. In this study, warpage issue of panel level fan-out package induced by molding based on 'Die Last' process is investigated. Warpage simulation and experiment are carried out by finite element method (FEM) and shadow moire, respectively. A novel warpage simulation method is presented for large area panel or wafer level simulation. In order to verify the accuracy and precision of the simulation method, a molded panel sample without dies is fabricated, and warpage experiment is carried out by shadow moire. Simulation and experimental result are compared with good agreement. © 2016 IEEE.


Hall D.,University of California at San Diego | Li B.,CAS Institute of Microelectronics | Li B.,National Center for Advanced Packaging China | Liu Y.-H.,University of California at San Diego | And 2 more authors.
Optics Letters | Year: 2015

Falling on the tail of the absorption spectrum of silicon, 1060 nm Si detectors often suffer from low responsivity unless an exceedingly thick absorption layer is used, a design that requires high operation voltage and high purity epitaxial or substrate material. We report an all-silicon 1060 nm detector with ultrahigh gain to allow for low operation voltage (<4 V) and thin (200 nm) effective absorption layer, using the recently discovered cycling excitation process. With 1% external quantum efficiency, a responsivity of 93 A/W was demonstrated in a p/n junction device compatible with the complementary metal-oxide-semiconductor process. © 2015 Optical Society of America.


He H.,National Center for Advanced Packaging China | He H.,CAS Institute of Microelectronics | Yu D.,CAS Institute of Microelectronics | Lin T.,National Center for Advanced Packaging China | And 2 more authors.
16th International Conference on Electronic Packaging Technology, ICEPT 2015 | Year: 2015

In this paper, a new micro-bump formation process was investigated by simulation method. In detail, a solder filling fixture was fabricated to hold the solder paste or alloy over the photoresist openings. As the fixture moves along the wafer surface, the solder paste or alloy was heated up to liquid status to fill in the photoresist openings under pressure force and vacuum circumstance. Then cooled down the temperature and solidified the molten solder to form the desired bumps. Before conduct the new bumping formation process, simulation work should be done to evaluate the process practicability and validation. Emphasis was placed on the simulation process construction to demonstrate the feasibility of the new bumping technology. Different influencing factors that may affect the bumping quality were studied such as the wall thickness of the filling fixture, gap between the wafer and the filling fixture, filling pressure, movement velocity of the filling fixture, and so on. In conclusion, an optimal filling parameter was obtained based on the simulation result. Future work will concentrate on the filling tests to verify the simulation results. © 2015 IEEE.


Xie H.,CAS Institute of Microelectronics | Li J.,CAS Institute of Microelectronics | Li J.,National Center for Advanced Packaging China | Song J.,CAS Institute of Microelectronics | And 10 more authors.
Proceedings - 2013 14th International Conference on Electronic Packaging Technology, ICEPT 2013 | Year: 2013

Portable consumer electronics have a tremendous demand of miniaturization, high density and high performance. 3D SIP is an efficient solution to meet this requirement. This paper had presented an innovative 3D package product configured with stacked die and cavity-embedded substrate. Through hole via in the substrate provides the signal communication at a cost-effective way. This structure satisfies the high standards for mobile products packaging by reducing the package size and cost and maintaining functionality. In this paper, some details on the design concepts of the structure are introduced. Then, since the geometric configuration of the bonding wire is unusual, the electrical performance of the wire bonds of the structure is predicted by HFSS. Though the wire bond is long, simulation results shows that it is still suitable for the speed circuits below 3GHz. On the other hand, the two-step cavity effectively improves the isolation capability between different die. Moreover, the fabrication process of this structure is presented in detail to access the design. Finally, the functional test of the end products is performed and the end products work well. © 2013 IEEE.


Qiu D.,CAS Institute of Microelectronics | Cao L.,CAS Institute of Microelectronics | Cao L.,National Center for Advanced Packaging China | Wu X.,CAS Institute of Microelectronics | And 6 more authors.
Proceedings - Electronic Components and Technology Conference | Year: 2015

3D stacked dies structure is a promising architecture to realize small feature size and enhanced electronic performance. However, its thermal dissipating performance for high density integration has aroused extensive attention. In this paper, a 3D stacked structure for thermal behavior investigation is presented. The vertical temperature profile of the stacked structure is obtained. A thermal resistance network and a finite element model have been built to fit the experiment data. Thermal management for the 3D stacked structure also is studied by air force cooling and immersion de-ionized (DI) water cooling. A good agreement between models and experiments is observed, while the temperature difference between models and experiments is within 5%. Under the air force convection and immersion cooling, the highest temperature point to ambient thermal resistance of the 3D stacked structure decreases to 7.6°C/W and 1°C/W respectively. © 2015 IEEE.


Hou F.,CAS Institute of Microelectronics | Hou F.,National Center for Advanced Packaging China | Zhang X.,CAS Institute of Microelectronics | Zhang X.,National Center for Advanced Packaging China | And 8 more authors.
Proceedings - 2013 14th International Conference on Electronic Packaging Technology, ICEPT 2013 | Year: 2013

In this study, a 3D package module based on flexible substrate is proposed. In order to improve the thermo-mechanical reliability of the 3D package module, the simulation of the key manufacture process is more and more important. The key manufacture processes of the 3D substrate package module mainly include 2D chip assembly, under-filling, 3D substrate folding, die-attaching, molding, and ball grid array (BGA) drop and reflow. At the molding process, when molding compound is injected into the 3D package structure, it will contact with other parts of the module. Because the coefficient of thermal expansion (CTE) and Young's modulus of the molding compound vary with temperature during cooling down from molding temperature, and differ from other parts of the package, the effect of molding compound cooling down process on the reliability of 3D package module is necessary to investigate. This paper performs the thermo-mechanical reliability finite element method (FEM) simulation of the molding compound cooling down process from molding temperature 125 °C to room temperature 25 °C to predict the warpage of the 3D package module. In order to conduct the molding compound cooling down simulation correctly, this paper testes Young's modulus of molding compound dependent on time and temperature by using Dynamic Mechanical Analysis (DMA). The simulation result shows that the maximum deformation of the 3D package module is only 6.27 μm, which appears in the corner of the 3D package module. Therefore, the process doesn't lead to warpage of the 3D package module and the molding compound is suitable for the 3D package. Besides, the thermo-mechanical reliability FEM simulation of the 3D package module under thermal cycling (-40/125 °C) is evaluated to find out the stress and strain distribution of the 3D package module, the BGA and to predict the warpage, delamination, die cracking, solder joint cracking, excessive substrate deformation and cracking of the 3D package module. Because the solder is viscoplastic, the Anand constitutive model is applied to represent the nonlinear deformation behavior of solder. The simulation results indicate that the 3D package module has higher thermo-mechanical reliability. © 2013 IEEE.


Zhuang Y.,National Center for Advanced Packaging China | Zhuang Y.,CAS Institute of Microelectronics | Yu D.,CAS Institute of Microelectronics | Dai F.,National Center for Advanced Packaging China | And 3 more authors.
Proceedings of the Electronic Packaging Technology Conference, EPTC | Year: 2014

This paper presents a novel spray coating process for the forming of sidewall insulation of through silicon via (TSV) which was a challenging process in CMOS image sensor (CIS) packaging. In conventional way, silicon oxide by plasma enhanced chemical vapor deposition (PECVD) is chosen as insulation material. In this paper, one kind of phenolic aldehyde polymer is deposited on the sidewall of though silicon via with the diameter of 75μm and depth of 100μm by novel spray coating process. To avoid the failure of TSV sidewall insulation and electrical interconnection characteristic, the thickness of polymer on the sidewall should be not less than 2μm. To achieve the insulation layer thickness target value, the temperature of spray coating process temperature was adjusted to control the viscosity of polymer. After the process optimization, the minimum thickness of sidewall polymer insulation layer is over 2.5μm meanwhile the conformal coverage characters of sidewall insulation layers are promoted. © 2014 IEEE.


Zhuang Y.,National Center for Advanced Packaging China | Zhuang Y.,CAS Institute of Microelectronics | Yu D.,CAS Institute of Microelectronics | Dai F.,National Center for Advanced Packaging China | And 2 more authors.
Microsystem Technologies | Year: 2014

This paper presents a detailed study to perform low temperature spray coating polymer dielectric process with good conformal deposition on aspect ratio features (2:1) through silicon via (TSV) CMOS image sensor (CIS) wafer-level-packaging. In this study, one kind of phenolic aldehyde polymer is deposited on the sidewall of though silicon via by spray coating process. Individual conditions that affect the weak-point of polymer dielectric on the TSV sidewall and step coverage such as nitrogen gas pressure, polymer solution flow rate and temperature are investigated. The optimal condition is used to deposit into TSVs by spray coating process. The results turn to give excellent step coverage and satisfied weak-point (>2 µm) on the sidewall of though silicon via with the diameter of 65 µm and depth of 130 µm. © 2014 Springer-Verlag Berlin Heidelberg


Wang H.,National Center for Advanced Packaging China | Huang W.,National Center for Advanced Packaging China | Geng F.,National Center for Advanced Packaging China | Lu Y.,National Center for Advanced Packaging China | And 2 more authors.
International Conference and Exhibition on Device Packaging 2014 | Year: 2014

Package-on-package (PoP) structure is widely used in smart phones and tablets in which memory package is directly attached to the top of the application processor. As the market demands more speed and bandwidth, memory devices need more than 1000 I/Os to support future requirements. However?since the package size also becomes smaller and smaller, finer I/O pitch is absolutely required. Some previously reported new technology can achieve finer I/O pitch. For example, the Through Mold Vias (TMV) PoP by Amkor can achieve 0.3mm~0.4mm PoP ball pitch and the High Copper Pillar (HCP) PoP by Unimicron deliver the pitch to 0.2mm. However it increases the manufacturing cost. Using traditional mature technology can reduce manufacturing cost, but has limitation in finer I/O pitch. So, it demands a reasonable balance between design, process and cost to develop an applicable PoP structure. © 2014 IEEE.


Hao H.,National Center for Advanced Packaging China | He H.,National Center for Advanced Packaging China | Lu Y.,National Center for Advanced Packaging China
Proceedings of the Electronic Packaging Technology Conference, EPTC | Year: 2014

Alloying with a suitable amount of rare earth (RE) elements in Sn3.8Ag0.7Cu solder alloy has been reported to have beneficial effects on their physical and mechanical properties. However, large sized RE-Sn phases, when adding excessive RE elements, will precipitate in the matrix of the solder. It is interesting to note that RE-Sn phases, when exposed in air, will be oxidized and rapid tin whisker growth will simultaneously appear on the surface of the oxidized RE-Sn phase. Moreover, it can be interpreted that the compressive stress resulting from the oxidation of RE-Sn phases provides the driving force for tin whisker growth, and the tin atoms released from the oxidation of RE-Sn phases becomes the growing source for tin whisker growth. So the mechanism for tin whisker growth on the surface of the oxidized RE-Sn phases can be established as follows: firstly 'tin whisker nuclei' are formed, secondly 'tin whisker nuclei' are pushed out of the surface to form baby tin whiskers, and finally baby tin whiskers will grow into the tin whiskers. Besides the past-reported rod-like, needle-like, thread-like tin whiskers, some tin whiskers with very special morphology, such as chrysanthemum-shaped whisker; spiral whisker; plate-like whisker; branch-type whisker; joint-type whisker and whiskers with a non-constant cross section were also found in this study. Importantly, the finding of tin whiskers with a non-constant cross section break the consensus of the past research, in which tin whisker should present constant cross section. Because the famous energy equations for tin whisker growth proposed by K.N. Tu could not explain the cross section changing phenomenon with some limitations. By analyzing the growing characteristic of tin whiskers on the surface of the oxidized RE-Sn phases, Tu's energy equations were modified and one kind of mechanism for cross section changing of tin whisker was proposed as follows: the incoordination between the growth rate and the tin atoms supply results in the cross section changing phenomenon. Finally, based on the study of tin whisker growth mechanism on the surface of the oxidized RE-Sn phase, and combined with recrystallization mechanism and oxide layer rupture mechanism, a 'double stress zone' model for tin whisker growth was proposed as follows: the 'low stress zone' and the 'high stress zone' are required for tin whisker growth. The stress zone located around the root is 'low stress zone' and the stress zone connected with the 'low stress zone' is the 'high stress zone'. The 'low stress zone' will provide the driving force for tin whisker growth, and the stress gradient between 'low stress zone' and 'high stress zone' will provide the tin atoms for tin whisker growth. © 2014 IEEE.

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