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Zhang H.Y.,Shanghai University | Yan X.,Shanghai University | Zhu W.H.,Central South University | Lin L.,National Center for Advanced Packaging
ASME 2015 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems, InterPACK 2015, collocated with the ASME 2015 13th International Conference on Nanochannels, Microchannels, and Minichannels | Year: 2015

5-D package with through silicon vias (TSVs) on interposer has been envisioned as the most viable way in heterogeneous integration. In this work, several design approaches are considered in the thermal analysis and enhancements of a 2.5-D package with multi chips on through silicon interposer (TSI), which include overmolding materials, metal slug, lid attachment, pin fin heat sink and fan-driven heat sink cooling. The analysis models consist of two dummy flip chips on a silicon interposer to represent the logic die and memory die, respectively. Package submodels, especially the TSV ones, are analyzed with good modeling accuracy. Package thermal modeling indicates that the thermal conductivity of the epoxy overmolding has minimal effect on the thermal performance of copper slug package. Lid attachment further enhances the thermal performance through peripheral substrate attachment. Both designs largely rely on thermally conductive PCB (4L) to maximize power dissipation. Pin-fin heat sink, made of aluminum, can be mounted on the package top to further minimize thermal resistance and extend the power dissipation beyond 10W. For high power application, fan cooled heat sink is used to reduce excessive heat. Copper based aluminum heat sink can remove the heat of 120W from the bare-die package. Self heating due to high current density through the TSV is analyzed. The proposed analytical expression gives good prediction on the local TSV hot spot. It is demonstrated that a distributed TSV network design provides lower temperature rise, which shall have lower risk of failures and is preferred in practice. © Copyright 2015 by ASME.


Liu H.,National Center for Advanced Packaging | Jiang F.,National Center for Advanced Packaging | Xue K.,National Center for Advanced Packaging | Yu D.,Huatian Technology Xian Co. | Liu X.,Wuxi Institute of Technology
16th International Conference on Electronic Packaging Technology, ICEPT 2015 | Year: 2015

Just in few years, three-dimensional (3D) packaging technologies have attracted much more attention. With the development of through-silicon via (TSV) technology, silicon-based device integrations have become the main stream of 3D packaging technologies. In this study, the assembly of high performance processor chip and TSV interposer is developed. From bottom to top assembly process was applied and the warpage of the interposer was effectively suppressed. Flying-Probe testing showed a good conducting of the package. © 2015 IEEE.


Lin L.,Fudan University | Wang J.,Fudan University | Wang L.,Fudan University | Wang L.,National Center for Advanced Packaging | And 3 more authors.
Microelectronics Reliability | Year: 2016

Using low-k/ultralow-k (LK/ULK) materials as the inter-layer dielectrics (ILD) and inter-metal dielectrics (IMD) in copper connections were implemented to meet the electrical performance requirements in the advanced chips. ULK materials are fragile and the mechanical failures in ULK materials are critical during chip packaging processes, such as the solder reflow in the flip-chip. A crack or delamination that initiates within the high thermo-mechanical stress regions can propagate into the active area of the chip in packaging, which involves the chip-packaging interaction (CPI) problem. In this study, we proposed a three-dimensional sub-modeling finite element approach considering an effective layer for the back end of line (BEOL) microstructures in the global model to improve the accuracy. The approach surmounted the difficulty of the large size difference between the chip and the ULK layers in computations. The stress analysis and parametric studies for a designed ULK chip with 40 nm technical node under the flip-chip reflow was performed based on the present method. The effects of the selected parameters were ranked and the optimal combination of the factors was achieved. © 2016 Elsevier Ltd


Zhang H.Y.,Shanghai University of Engineering Science | Wang Y.S.,Shanghai University of Engineering Science | Zhu W.H.,Central South University | Lin T.,National Center for Advanced Packaging
16th International Conference on Electronic Packaging Technology, ICEPT 2015 | Year: 2015

Device scaling and heterogeneous integration necessitate through silicon vias (TSVs) as interconnects for 2.5D and 3D chip packages for shortened signal transmission, less delay, and more functionality. Proper evaluation of the thermal properties of TSVs is a key to the successful design of the package. On the other hand, the determination of in-plane thermal conductivity is complicated with the thin insulation materials made of silicon oxide or polymers surrounding the TSV, which is not well addressed in previous studies. In the present work, effort is made to develop a closed-form effective thermal conductivity model for the TSV array by treating the insulation material as the contact resistance. The present model takes into account the sizes and thermal conductivities of the constituents, which is able to predict the in-plane thermal conductivity with reasonable agreement in comparison with the numerical computation. Furthermore, the effect of the transverse heat conduction is examined in a package with a thermal test die on a silicon interposer and substrate. The numerical computation shows that, by taking into account the effect of insulation material, the package thermal resistance could increase by 7.3%. © 2015 IEEE.


Lin L.,Fudan University | Wang J.,Fudan University | Wang L.,National Center for Advanced Packaging | Zhang W.,National Center for Advanced Packaging
16th International Conference on Electronic Packaging Technology, ICEPT 2015 | Year: 2015

Using ultralow-k (ULK) materials as inter-layer dielectrics (ILD) and inter-metal dielectrics (IMD) in copper connections were implemented to meet the electrical performance requirements in the advanced chips. ULK materials become fragile because tiny pores and inclusions were introduced to reduce the dielectric constant (k). As a result, the mechanical failures in ULK materials are critical during packaging processes, such as solder reflow. In this study, the stress analysis and parametric study for a designed ULK chip under the flip chip reflow was performed by finite element method with sub-modeling technology. The microstructures on the surface of chip, including ULK materials, were homogenized to an effective thin layer and equivalent material properties were used in the global model analysis. The ULK/Cu structures under the corner joint that suffering higher stresses was analyzed by the sub-modeling method. The local model including M1 - M10 Cu/ULK connection and dielectric layers and the stresses can be achieved. Using the method, the effect of design parameters, e.g. PI opening, copper pillar diameter and Ni thickness, was examined by comparing the stress in the ultralow-k dielectric layers. The results reveal a decreased risk for a design with the smaller PI opening, larger copper pillar diameter and adding the Ni layer. © 2015 IEEE.


Song C.,National Center for Advanced Packaging | Song C.,CAS Institute of Microelectronics | Zhang W.,National Center for Advanced Packaging | Shangguan D.,National Center for Advanced Packaging | Shangguan D.,CAS Institute of Microelectronics
Proceedings of 2014 4th IEEE International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2014 | Year: 2014

This paper discusses the application of conductive wafer bonding, especially wafer level hybrid Cu-Cu bonding, for realizing high density inter-chip interconnection. 3D integration process using conductive wafer bonding and the test vehicle for bonding process evaluation are described. Different pre-bonding surface treatment methods and bonding procedures are studied and compared for yield and throughput optimization. © 2014 IEEE.


Zhang W.,National Center for Advanced Packaging
Japanese Journal of Applied Physics | Year: 2015

Three-dimensional (3D) integration requires vertical stacking of dies while forming permanent electrical and mechanical connections between the input/output pins of the devices. How to enable stacking thermal sensitive devices at low temperature gains interest. This paper presents a systematic study of Cu/Sn bonding at 150-200°C, during which intermetallic compounds were formed by solid state inter-diffusion. It was found that below the lower-limit pressure of 20MPa it was hard to make good contact between the rough joint surfaces and hence electrical connection was lost. However, beyond the upper-limit of 150MPa Sn squeezed out leading to electrical shorting between adjacent bumps. Oxides removal was another key factor for good bonding. Finally, this Cu/Sn solid state diffusion bonding together with Cu through-silicon-via (TSV) was used for making die to die vertical interconnection. The measured resistance of single Cu/Sn solder joint and Cu TSV was in the range of 12-25 mΩ. © 2015 The Japan Society of Applied Physics.


Li Z.,National Center for Advanced Packaging | Jing X.,National Center for Advanced Packaging | Jiang F.,National Center for Advanced Packaging | Zhang W.,National Center for Advanced Packaging
Proceedings of the Electronic Packaging Technology Conference, EPTC | Year: 2014

TSV (through silicon via) is regarded as a key technology for 2.5D and 3D electronic packaging. And the manufacturing of the through silicon interposer is very challenge and costly. In the backside process of interposer, grinding is considered as the most promising technology to control wafer's surface roughness and surface defect. In this paper, according to the grinding process, a mathematical model is established. According to the model, MATLAB is used to simulate and predict the grinding marks and the distance between two adjacent grinding lines during the backside grinding process. The grinding marks of the half contact grinding model and full contact grinding model with different wheel rotation speed and wafer rotation speed are presented. And the relationship between two adjacent grinding lines and the ratio of wafer rotation speed and wheel rotation speed is predicted. The experiments are also carried out to verify the proposed model. The results of the experiments agree well with the simulation results. © 2014 IEEE.


Dai F.,National Center for Advanced Packaging | Niu Z.,National Center for Advanced Packaging | Zhang W.,National Center for Advanced Packaging
Proceedings of the Electronic Packaging Technology Conference, EPTC | Year: 2014

TSV CIS package technology is based on a via-last approach in association with an adapted bonding for optical applications. With the gradual increase of the CIS pixel and package integration density, CIS packaging requirements are also increasing. High aspect ratio TSV advantage is gradually reflected. The 3D stacking technology with TSV will be the future development trend of CIS package. In order to complete the bottom of the TSV etch process, we need to protect the wafer surface dielectric layer. In this paper, we use aluminum as a mask to protect the wafer surface silicon oxide dielectric layer. Aluminum with the thickness of 150nm doesn't meet the requirement of the silicon oxide of TSV bottom etching. However, Aluminum with the thickness of 200nm and 300nm can play a role of the etching mask. And Aluminum mask with the thickness of 300nm can withstand 400s of etching time. © 2014 IEEE.


Lu Y.,National Center for Advanced Packaging | Lu Y.,CAS Institute of Microelectronics | Yin W.,National Center for Advanced Packaging | Yin W.,CAS Institute of Microelectronics | And 11 more authors.
Proceedings - Electronic Components and Technology Conference | Year: 2013

Just in few years, three-dimensional (3D) packaging technologies have attracted much more attention. With emergence of through-silicon via (TSV) technology, silicon-based device integrations, the TSV's, have become the main stream of 3D packaging technologies. TSV's can be further classified as 2.5D and 3D TSV's. For 2.5D TSV package assembly, since multiple components involved, there are normally two assembly process approaches, i.e., from 'Top-to-Bottom' (TOB), or from 'Bottom-to-Top (BOT). Each approach has its own pros and cons. From stress minimization aspect, TOB is more desirable. But from packaging assembly easiness viewpoint, BOT is more practical and thus has been mainly utilized. To overcome these dilemmas occurred in 2.5D TSV package assembly, a new assembly process approach, called new TOB (n-TOB), has been developed. Instead of bonding the chip onto the interposer, the n-TOB starts out with precisely bonding the interposer onto the chip with using a specially-designed eccentric-axis pickup tip which also effectively protects the flip chip C4 bumps on the interposer backside during bonding. Finite-element (FE) simulation and reliability tests were employed to assess the effectiveness and impact of this new assembly approach on 2.5D TSV packages. The assessment results show that n-TOB is feasible with at least the same performance in both package assembly and reliability. © 2013 IEEE.

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