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Zhang H.Y.,Shanghai University | Yan X.,Shanghai University | Zhu W.H.,Central South University | Lin L.,National Center for Advanced Packaging
ASME 2015 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems, InterPACK 2015, collocated with the ASME 2015 13th International Conference on Nanochannels, Microchannels, and Minichannels | Year: 2015

5-D package with through silicon vias (TSVs) on interposer has been envisioned as the most viable way in heterogeneous integration. In this work, several design approaches are considered in the thermal analysis and enhancements of a 2.5-D package with multi chips on through silicon interposer (TSI), which include overmolding materials, metal slug, lid attachment, pin fin heat sink and fan-driven heat sink cooling. The analysis models consist of two dummy flip chips on a silicon interposer to represent the logic die and memory die, respectively. Package submodels, especially the TSV ones, are analyzed with good modeling accuracy. Package thermal modeling indicates that the thermal conductivity of the epoxy overmolding has minimal effect on the thermal performance of copper slug package. Lid attachment further enhances the thermal performance through peripheral substrate attachment. Both designs largely rely on thermally conductive PCB (4L) to maximize power dissipation. Pin-fin heat sink, made of aluminum, can be mounted on the package top to further minimize thermal resistance and extend the power dissipation beyond 10W. For high power application, fan cooled heat sink is used to reduce excessive heat. Copper based aluminum heat sink can remove the heat of 120W from the bare-die package. Self heating due to high current density through the TSV is analyzed. The proposed analytical expression gives good prediction on the local TSV hot spot. It is demonstrated that a distributed TSV network design provides lower temperature rise, which shall have lower risk of failures and is preferred in practice. © Copyright 2015 by ASME. Source


Zhang W.,National Center for Advanced Packaging
Japanese Journal of Applied Physics | Year: 2015

Three-dimensional (3D) integration requires vertical stacking of dies while forming permanent electrical and mechanical connections between the input/output pins of the devices. How to enable stacking thermal sensitive devices at low temperature gains interest. This paper presents a systematic study of Cu/Sn bonding at 150-200°C, during which intermetallic compounds were formed by solid state inter-diffusion. It was found that below the lower-limit pressure of 20MPa it was hard to make good contact between the rough joint surfaces and hence electrical connection was lost. However, beyond the upper-limit of 150MPa Sn squeezed out leading to electrical shorting between adjacent bumps. Oxides removal was another key factor for good bonding. Finally, this Cu/Sn solid state diffusion bonding together with Cu through-silicon-via (TSV) was used for making die to die vertical interconnection. The measured resistance of single Cu/Sn solder joint and Cu TSV was in the range of 12-25 mΩ. © 2015 The Japan Society of Applied Physics. Source


Zhang H.Y.,Shanghai University of Engineering Science | Wang Y.S.,Shanghai University of Engineering Science | Zhu W.H.,Central South University | Lin T.,National Center for Advanced Packaging
16th International Conference on Electronic Packaging Technology, ICEPT 2015 | Year: 2015

Device scaling and heterogeneous integration necessitate through silicon vias (TSVs) as interconnects for 2.5D and 3D chip packages for shortened signal transmission, less delay, and more functionality. Proper evaluation of the thermal properties of TSVs is a key to the successful design of the package. On the other hand, the determination of in-plane thermal conductivity is complicated with the thin insulation materials made of silicon oxide or polymers surrounding the TSV, which is not well addressed in previous studies. In the present work, effort is made to develop a closed-form effective thermal conductivity model for the TSV array by treating the insulation material as the contact resistance. The present model takes into account the sizes and thermal conductivities of the constituents, which is able to predict the in-plane thermal conductivity with reasonable agreement in comparison with the numerical computation. Furthermore, the effect of the transverse heat conduction is examined in a package with a thermal test die on a silicon interposer and substrate. The numerical computation shows that, by taking into account the effect of insulation material, the package thermal resistance could increase by 7.3%. © 2015 IEEE. Source


Su M.,CAS Institute of Microelectronics | Su M.,National Center for Advanced Packaging | Yu D.,CAS Institute of Microelectronics | Yu D.,National Center for Advanced Packaging | And 10 more authors.
Thin Solid Films | Year: 2014

The dielectric via liner of through silicon vias was deposited at 400 C using a tetraethyl orthosilicate (TEOS)-based plasma enhanced chemical vapor deposition process in a via-middle integration scheme. The morphology, conformality and chemical compositions of the liner film were characterized using field emission scanning electron microscopy and Fourier Transform Infrared spectroscopy. The thermal properties and electrical performance of blanket TEOS films were investigated by high temperature film stress and mercury probe Capacitance-Voltage measurements. The TEOS SiO2 films show good conformality, excellent densification, low thermal stress, high breakdown voltage and low current leakage. © 2013 Elsevier B.V. Source


Lin L.,Fudan University | Wang J.,Fudan University | Wang L.,National Center for Advanced Packaging | Zhang W.,National Center for Advanced Packaging
16th International Conference on Electronic Packaging Technology, ICEPT 2015 | Year: 2015

Using ultralow-k (ULK) materials as inter-layer dielectrics (ILD) and inter-metal dielectrics (IMD) in copper connections were implemented to meet the electrical performance requirements in the advanced chips. ULK materials become fragile because tiny pores and inclusions were introduced to reduce the dielectric constant (k). As a result, the mechanical failures in ULK materials are critical during packaging processes, such as solder reflow. In this study, the stress analysis and parametric study for a designed ULK chip under the flip chip reflow was performed by finite element method with sub-modeling technology. The microstructures on the surface of chip, including ULK materials, were homogenized to an effective thin layer and equivalent material properties were used in the global model analysis. The ULK/Cu structures under the corner joint that suffering higher stresses was analyzed by the sub-modeling method. The local model including M1 - M10 Cu/ULK connection and dielectric layers and the stresses can be achieved. Using the method, the effect of design parameters, e.g. PI opening, copper pillar diameter and Ni thickness, was examined by comparing the stress in the ultralow-k dielectric layers. The results reveal a decreased risk for a design with the smaller PI opening, larger copper pillar diameter and adding the Ni layer. © 2015 IEEE. Source

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