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Santa Clara, CA, United States

Patent
Nanya Technology Corporation | Date: 2015-01-07

A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.


Patent
Nanya Technology Corporation | Date: 2015-05-07

A circuit in dynamic random access memory devices includes a command extension circuit. The command extension circuit is configured to generate at least one multiple-cycle command signal by lengthening a single-cycle clock command signal from a command decoding circuit. Control logic extends and reduces the multiple-cycle command signal to provide additional functions such as burst length and burst chop. Additional control logic is configured to determine whether a clock signal is enabled in output control logic circuitry according to the multiple-cycle command and logic level generated in the output logic circuitry.


Patent
Nanya Technology Corporation | Date: 2014-04-09

A capacitor includes a substrate, a multilayer over the substrate, a plurality of container-shaped storage node structures on the semiconductor substrate and surrounded by the multilayer, the storage node structure has a sidewall extending upwardly from the base to the top, where the sidewall includes an upper segment and a lower segment thinner than the upper segment, a capacitor dielectric material along a surface of each storage node structure, and a capacitor electrode material over the capacitor dielectric material.


Patent
Nanya Technology Corporation | Date: 2015-02-09

A trench extends from a main surface of a semiconductor substrate to a predetermined depth. A gate oxide layer is formed in the trench. A buried gate electrode is formed at a lower portion of the trench. The buried gate electrode is capped with a dielectric layer. A pad layer and hard mask layer are formed on the semiconductor substrate. A recess through the pad layer and hard mask layer and into the semiconductor substrate is formed on one side of the trench. A portion of the dielectric layer is revealed within the recess. The hard mask layer is then removed. An ion implantation process is performed to implant dopants on both sides of the trench, thereby forming a source doping region and a drain doping region. The source doping region has a junction depth that is deeper than that of the drain doping region.


A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate. The word line includes: a gate electrode, a gate dielectric layer disposed between the gate electrode and the substrate and at least one first charge trapping dielectric layer disposed adjacent to the gate electrode, wherein the first charge trapping dielectric layer comprises HfO

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