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Patent
Nanya Technology Corporation | Date: 2017-01-25

A semiconductor device includes a transistor disposed on a substrate, a first insulation layer, a second insulation layer, an epitaxy and a conductive material. The first insulation layer is disposed on the substrate and protruding over the transistor. The first insulation layer has a recess to expose a top portion of the transistor. The second insulation layer is disposed on the first insulation layer and conforms to the recess and exposes the top portion of the transistor. The epitaxy is disposed in the recess of the first insulation layer and overlaps the top portion of the transistor. The epitaxy conforms to sidewalls of the recess of the first insulation layer. The conductive material is disposed in the recess of the first insulation layer. The conductive material is electrically connected to the top portion of the transistor through the epitaxy,


Patent
Nanya Technology Corporation | Date: 2015-11-23

A dynamic random access memory circuit includes several memory cells, several word line drivers and a first voltage generator. The first voltage generator electrically coupled with the word line drivers, and the first voltage generator is configured to generate a first voltage signal to the word line drivers, in which during a self refresh period of the memory cells, the first voltage signal is decreased by the first voltage generator from a first level to a second level.


Patent
Nanya Technology Corporation | Date: 2015-12-03

A tray for holding an integrated circuit component includes a base frame and at least a pair of supporting walls. The supporting walls are connected to the base frame. The supporting walls are opposite to each other. Each of the supporting walls has a curved surface substantially facing to each other. The curved surfaces are configured to respectively support at least two portions of the integrated circuit component. A gap exists between the integrated circuit component and the base frame when the integrated circuit component is held by the curved surfaces.


Patent
Nanya Technology Corporation | Date: 2016-06-30

The invention provides a method for fabricating a semiconductor device, including: forming a dummy gate on a substrate, forming an inter-layer dielectric layer (ILD) on the dummy gate and the substrate, forming a metal layer on the upper surface of the dummy gate, removing the dummy gate to form a trench in the inter-layer dielectric layer (ILD), conformally forming a gate dielectric layer in the trench, conformally forming a first conductive type metal layer on the gate dielectric layer, anisotropic etching the first conductive type metal layer and the gate dielectric layer over the metal layer to form a gap in the inter-layer dielectric layer (ILD), and filling a second conductive type metal layer in the gap.


Patent
Nanya Technology Corporation | Date: 2016-06-08

An etching process in a capacitor process for DRAM is described. A substrate is provided, which has thereon a silicon layer and metal electrodes in the silicon layer. The silicon layer is removed using a liquid etchant composition. The liquid etchant composition contains tetramethylammonium hydroxide (TMAH), an additive including hydroxylamine or a metal corrosion inhibitor, and water as a solvent.


Patent
Nanya Technology Corporation | Date: 2015-05-07

A circuit in dynamic random access memory devices includes a command extension circuit. The command extension circuit is configured to generate at least one multiple-cycle command signal by lengthening a single-cycle clock command signal from a command decoding circuit. Control logic extends and reduces the multiple-cycle command signal to provide additional functions such as burst length and burst chop. Additional control logic is configured to determine whether a clock signal is enabled in output control logic circuitry according to the multiple-cycle command and logic level generated in the output logic circuitry.


Patent
Nanya Technology Corporation | Date: 2015-06-23

A method for forming a pattern includes steps of forming a patterned core layer on a substrate, conformally forming a spacer layer on the patterned core layer to form first concave portions, performing an etch back process to expose the patterned core layer, removing the exposed patterned core layer to form second concave portions, filling up the first concave portions and the second concave portions with a directed self-assembly material, and activating a directed self-assembly process, so that the directed self-assembly material is diffused to the perimeter of the concave portions to form a hole surrounding by the directed self-assembly material in each concave portions.


Patent
Nanya Technology Corporation | Date: 2016-06-27

The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.


Patent
Nanya Technology Corporation | Date: 2015-02-09

A trench extends from a main surface of a semiconductor substrate to a predetermined depth. A gate oxide layer is formed in the trench. A buried gate electrode is formed at a lower portion of the trench. The buried gate electrode is capped with a dielectric layer. A pad layer and hard mask layer are formed on the semiconductor substrate. A recess through the pad layer and hard mask layer and into the semiconductor substrate is formed on one side of the trench. A portion of the dielectric layer is revealed within the recess. The hard mask layer is then removed. An ion implantation process is performed to implant dopants on both sides of the trench, thereby forming a source doping region and a drain doping region. The source doping region has a junction depth that is deeper than that of the drain doping region.


Patent
Nanya Technology Corporation | Date: 2016-04-29

A wire bonding method includes the following steps. First, a substrate including at least one metal finger is provided. Next, a first chip including at least one first boding pad is disposed on the substrate. Next, a metal ball bump is foamed on the corresponding metal finger. Next, a first wire is formed from the metal ball bump toward the corresponding first boding pad. Next, a first free air ball is formed on the first wire by electronic flame-off process. Then, the first free air ball connected to the first wire is pressed on the corresponding first boding pad, such that the first wire is located between the first free air ball and the corresponding first boding pad.

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