Nano ENS Co.

Suigen, South Korea

Nano ENS Co.

Suigen, South Korea
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Wang C.,Kwangwoon University | Wang C.,Nano ENS Co. | Lee W.S.,Nano ENS Co. | Zhang F.,Kwangwoon University | Kim N.Y.,Kwangwoon University
International Journal of Advanced Manufacturing Technology | Year: 2011

A novel process is developed for fabricating cost-effective, high-yield, and high-quality integrated passive devices on SI-GaAs substrate. Various material and processing approaches to thin film resistors (TFRs), spiral inductors, and metal-insulator-metal (MIM) capacitors are evaluated in terms of cost, yield and device performance. For better precision in TFR resistance, we modify the bottom metal manufacturing process. For higher spiral inductor quality factor (Q-factor) and yield, a much thicker second metal and a sputter-etching process is presented. For higher MIM capacitor yield, some optimised mechanisms are used. To further decrease the cost and increase the yield, SU-8 photo resist is firstly presented as a novel material for forming the final passivation layer to replace the traditional SiNx. A wireless local area network balun, low-pass filter and digital cellular system power divider are demonstrated by using this novel manufacturing process; they show very good RF performances in spite of theirs small chip size and low cost, compared with those of the reported literature. © 2010 Springer-Verlag London Limited.


Cho S.J.,Kwangwoon University | Cho S.J.,Nano ENS Co. | Wang C.,Kwangwoon University | Wang C.,Nano ENS Co. | And 4 more authors.
Advanced Materials Research | Year: 2011

Double passivation layers, Si3N4 on Si 3N4 (Si3N4 / Si3N 4), have been implemented onto the top and bottom surface passivation film layers for a gamma-gate AlGaN/GaN HEMT using Plasma Enhanced Chemical Vapor Deposition (PECVD). The effects of the reduced current collapse electro characteristics were then compared to devices using double passivation as SiO2 on SiO2 (SiO2 / SiO2). Both samples were tested under the same conditions: Vds = 0 to 15 V and Vgs = 1 to -5 V. The Si3N4 / Si 3N4 passivation results show a maximum saturation current density (Ids max) of 761 mA/mm, a peak extrinsic trans conductance (gm max) of 200 mS/mm, and threshold voltages of (Vth) -4.5 V, which increases up to 18% and 5% than those of SiO2/SiO 2 double passivation. © (2011) Trans Tech Publications, Switzerland.


Wang C.,Kwangwoon University | Wang C.,Nano ENS Co. | Lee W.-S.,Kwangwoon University | Lee W.-S.,Nano ENS Co. | And 2 more authors.
Advanced Materials Research | Year: 2011

A novel silicon-based packaging platform with the electroplated-based reflector and the electrode-guided interconnections is developed for the packaging component of a high-luminosity and high-efficiency multi-chip light-emitting diode (LED) module, which is patterned on a new type of insulating layer that consists of nanoporous anodized aluminum oxide (AAO) layer and plasma-enhanced chemical vapor deposition (PECVD) deposited silicon dioxide (SiO2) on a doped silicon substrate. The reflector and the electrical interconnections are successfully fabricated by using the electroplating method in the same body. In order to obtain the benefits of high efficiency LED modules, the requirements concerning thermal management and photomechanical layout have to be met. In this paper, we will discuss a novel fabrication method in LED module packaging platform, and then describe the thin layer of electroplated Cu/Ni/Au in order to reduce thermal resistance and to increase thermal diffusion efficiency. The heat generated by the LED chips is dissipated directly to the silicon body through the metal-plated platform, and truly excellent heat dissipation characteristics are observed. We demonstrate 987 lm 8 W-level cool-white light (5000 K, 16 V, 110 lm/W, CRI = 77) emission for 570 μm × 230 μm-chip LEDs at 600 mA operation. © (2011) Trans Tech Publications, Switzerland.


Wang C.,Kwangwoon University | Wang C.,Nano ENS Co. | Lee W.S.,Nano ENS Co. | Kim N.Y.,Kwangwoon University
IEEE MTT-S International Microwave Symposium Digest | Year: 2010

A novel fabrication process has been demonstrated to create cost-effective, high-yield, and high-quality integrated passive devices (IPDs) on GaAs substrate. Various materials and processing approaches to thin film resistors (TFRs), spiral inductors, and metal-insulator-metal (MIM) capacitors have been evaluated in terms of cost, yield, and device performance. To further reduce the total cost, SU-8 photo resist (PR) is firstly presented as a novel material for forming the final passivation layer. A digital cellular system (DCS) power divider is realized by this novel process and shows very good RF performances with the high yield and low cost in spite of its small chip size. © 2010 IEEE.


Wang C.,Kwangwoon University | Wang C.,Nano ENS Co. | Cho S.J.,Kwangwoon University | Cho S.J.,Nano ENS Co. | And 4 more authors.
International Journal of Advanced Manufacturing Technology | Year: 2013

In this paper, the development of a novel manufacturing process is presented for fabricating high-quality AlGaN/GaN high-electron-mobility transistors (HEMTs) on Si (111) substrates. Various material and processing approaches regarding surface passivation, gate oxide, ohmic contact metal, and post-gate annealing are evaluated in terms of device performance. In order to achieve better immunity to current collapse effects, we conducted experiments that investigate the relationship between the AlGaN/GaN HEMTs' electrical characteristics and different passivation films by plasma-enhanced chemical vapour deposition. In order to obtain a better ohmic contact performance, we tested a Ti/Al/Ta/Au ohmic contact metallisation scheme using different annealing temperatures and annealing times to achieve a lower contact resistance, a more proper line edge definition, and a better surface morphology. A post-gate N2 rapid thermal annealing method done after the gate metallisation process has shown better DC current-voltage output, transfer characteristics, and gate-drain breakdown voltage results compared to the as-fabricated HEMTs. A HEMT with a 0.5-μm gate length, exhibiting a maximum drain current density of 750 mA/mm, a peak transconductance of 220 mS/mm, a unity-gain cut-off frequency of 24.6 GHz, and a maximum frequency of oscillation of 45.4 GHz, was fabricated using this novel manufacturing process; the X-band power performances demonstrate a 5.8-W/mm output power density and a 51 % power-added efficiency. © 2012 Springer-Verlag London.


Wang C.,Kwangwoon University | Lee W.S.,Nano ENS Co. | Cho S.J.,Kwangwoon University | Kim N.Y.,Kwangwoon University
Electronics Letters | Year: 2012

A physical dicing method for realising backside source grounding is first proposed for high-power microwave AlGaN/GaN high electron mobility transistors (HEMTs) on 4-inch 477m-thick silicon carbide (SiC) substrates. The successful implementation of the dicing-assisted source grounding technology in the processing of HEMTs is confirmed by DC and RF characterisation. When biased at 30V, a 10GHz output power density of 9.18W/mm is achieved with an associated gain of 9.6dB and power added efficiency of 50 for a 2×(200×0.5) μm 2 AlGaN/GaN HEMT with backside source grounding. © 2012 The Institution of Engineering and Technology.


Wang C.,Kwangwoon University | Wang C.,NanoENS Co. | Lee W.-S.,Kwangwoon University | Lee W.-S.,NanoENS Co. | And 2 more authors.
Microwave Journal | Year: 2012

An integrated passive device (IPD) technology has been developed in order to achieve lower cost, miniaturization and higher performance in RF and microwave devices applied to the front-end modules of wireless communication systems. Various kinds of high performance IPDs have been fabricated on a six inch GaAs wafer due to the well-developed, low cost RF passive manufacturing technology. Since this article is primarily about the practical design and fabrication of IPDs, it will discuss topics such as IPD fabrication technology, design flow, schematic circuit design and 3D EM simulation. Different kinds of IPDs such as baluns, power dividers, lowpass filters (LPF), and their measurement results are presented.


Wang C.,Kwangwoon University | Lee W.S.,Nano ENS Co. | Zhang F.,Kwangwoon University | Kim N.Y.,Kwangwoon University
Electronics Letters | Year: 2010

A method for fabricating a Si-based packaging platform with a reflector and electrode-guided interconnections is proposed for the packaging component of a high-power light-emitting diode (LED) module. The reflector is fabricated by Ni/Au/Ag-electroplating which is patterned by SU-8 2075 and 4620 negative photo-resistors and the electrical interconnections are formed by Cu/Au-electroplating in the same body. The heat generated by the LED chip is dissipated directly to the Si body through the large metal-plated platform. This method is suitable for high-efficiency and low-cost LED packaging. © 2010 The Institution of Engineering and Technology.

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