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Ye Z.,Nanjing Southeast University | Wang Z.,Nanjing Southeast University | Wu Y.,Nanjing Southeast University | Chen J.,Nanjing Ticom Technology Co.
2014 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2014 | Year: 2014

A current-mode active-RC filter is presented in this paper. With the center frequency of 2MHz and bandwidth 1.6MHz,the filter is a 3rd order complex band-pass filter. A fully differential current amplifier (FDCA) based on second-generation current conveyor (CCII) is introduced. Furthermore, programmable capacitor array and adjustable DC bias are used to help tuning the filter. The filter is designed in full custom design flow with standard SMIC 0.18μm CMOS technology. Post simulation results exhibit that the GF (gain flatness) of passing-band is within 2.5dB, IRR (image reject ratio) and ACS (adjacent channel selectivity) both exceed 35dB. © 2014 IEEE. Source


Xu J.,Nanjing Southeast University | Zhou Z.,Nanjing Southeast University | Wu Y.,Nanjing Southeast University | Wang Z.,Nanjing Southeast University | Chen J.,Nanjing Ticom Technology Co.
Journal of Semiconductors | Year: 2015

A passive current switch mixer was designed for the second IF down-conversion in a DRM/DAB receiver. The circuit consists of an input transconductance stage, a passive current switching stage, and a current amplifier stage. The input transconductance stage employs a self-biasing current reusing technique, with a resistor shunt feedback to increase the gain and output impedance. A dynamic bias technique is used in the switching stage to ensure the stability of the overdrive voltage versus the PVT variations. A current shunt feedback is introduced to the conventional low-voltage second-generation fully balanced multi-output current converter (FBMOCCII), which provides very low input impedance and high output impedance. With the circuit working in current mode, the linearity is effectively improved with low supply voltages. Especially, the transimpedance stage can be removed, which simplifies the design considerably. The design is verified with a SMIC 0.18 μm RF CMOS process. The measurement results show that the voltage conversation gain is 1.407 dB, the NF is 16.22 dB, and the IIP3 is 4.5 dBm, respectively. The current consumption is 9.30 mA with a supply voltage of 1.8 V. This exhibits a good compromise among the gain, noise, and linearity for the second IF mixer in DRM/DAB receivers. © 2015 Chinese Institute of Electronics. Source


Xu J.,Nanjing Southeast University | Peng B.,Nanjing Southeast University | Wang Z.,Nanjing Southeast University | Chen J.,Nanjing Ticom Technology Co.
Proceedings of 2015 IEEE International Conference on Communication Software and Networks, ICCSN 2015 | Year: 2015

An active CMOS mixer based on Gilbert cell was designed for the 2nd IF conversion in DRM/DAB receiver. Differential multiple gate transistors (DMGTR) combined with dynamic current injection technique was adopted to improve the noise and linearity performance respectively. The design was verified with SMIC0.18μm RF CMOS process. The simulated results show that the voltage conversation gain is 7.2dB and 7.12dB, the NF is 12.8dB and 12.28dB, the IIP3 is 18.05dBm and 19.62dBm for the DRM and DAB standards respectively. The power consumption is 5.9mW with a supply voltage of 1.8V. It exhibits a good compromise between the gain, noise and linearity for the 2nd IF mixer in DRM/DAB receivers. © 2015 IEEE. Source


Tian M.,Nanjing Southeast University | Wang Z.,Nanjing Southeast University | Xu J.,Nanjing Southeast University | Ji R.,Nanjing Ticom Technology Co. | Chen J.,Nanjing Ticom Technology Co.
Analog Integrated Circuits and Signal Processing | Year: 2015

A novel low-IF double balanced CMOS Gilbert mixer with high linearity and conversion gain is presented in this paper. An innovative easy-implemented cross-coupled full differential multiple gated transistor topology is proposed to improve the linearity while maintaining the high conversion gain. In addition, a topology, which artfully combines the current-bleeding technology and the noise-cancelling technology, is introduced to reduce the noise figure. The prototype of the proposed circuit was fabricated in SMIC 0.18 μm CMOS process with a chip area of 0.32 × 0.24 mm2. The measurement results have exhibited an IIP3 of 10.2 dBm and a conversion gain of 17.8 dB with a power dissipation of 3.6 mW from 1.8 V supply. Compared to recently published studies, the proposed work has achieved a higher FoM. © 2015, Springer Science+Business Media New York. Source

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