Nanjing Changfeng Aerospace Electronic Technology Co.

Nanjing, China

Nanjing Changfeng Aerospace Electronic Technology Co.

Nanjing, China
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Peng H.,Hunan University of Technology | Peng H.,Nanchang University | Zhao J.,Nanjing Changfeng Aerospace Electronic Technology Co. | Zhang H.,Nanjing Changfeng Aerospace Electronic Technology Co. | And 4 more authors.
Progress In Electromagnetics Research M | Year: 2014

A novel approach to design microstrip ultra-wideband (UWB) bandpass filter (BPF) using modified genetic algorithm (MGA) is proposed in this paper. To achieve high efficiency and accuracy, conventional GA is modified. By improving the fitness evaluation, selection, crossover, and mutation, the two possible drawbacks of conventional GA, i.e., slow rate of convergence and local-best solution, are overcome. The modified genetic algorithm is then applied to simultaneously search for the appropriate circuit topology and the corresponding electrical parameters with UWB characteristic. To demonstrate the effectiveness of the novel approach, a new microstrip UWB BPF is designed and fabricated. Measurement results agree well with the design index and full-wave EM simulated results.


Quan Z.,Zhengzhou University | Liu J.,Nanjing ChangFeng Aerospace Electronic Technology Co. | Zakharov Y.,University of York
Circuits, Systems, and Signal Processing | Year: 2015

An M-ary PSK detector, named multiple-phase detector (MPD), is presented that is efficient for both MIMO and multiuser detection, particularly when the number of transmit antennas/users is high. The detector is based on a novel iterative phase descent search (PDS) algorithm. The PDS algorithm arrives at a solution using coordinate descent iterations, where coordinates are the unknown symbol phases, and the solution is constrained to a unit magnitude. In the MPD, the PDS is used multiple times with different initializations; the solution with the minimum cost is then chosen as the final MPD solution. Numerical results show that in a variety of scenarios the MPD performance is close to the optimal performance, whereas its complexity is lower than that of advanced techniques. We present a hardware architecture and FPGA implementation of the MPD. The proposed architecture maximizes the processing speed and minimizes the programmable logic resources. The proposed design requires as few as about $$330$$330 Xilinx logic slices for $$32\times {32}$$32×32 and $$64\times {64}$$64×64 MIMO systems and supports a speed of 450 MHz. The fixed-point implementation demonstrates a detection performance which is very close to the performance of the floating point counterpart. © 2014, Springer Science+Business Media New York.

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