Hsinchu, Taiwan
Hsinchu, Taiwan

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Patent
MStar Semiconductor Inc. | Date: 2016-03-23

An LDO with high efficiency receives an input voltage from an input power line and outputs an output voltage at an output power line. The LDO includes a first active device, a second active device, an operational amplifier and a protection circuit. The first and second active devices are connected in series between the input and output power lines via a connecting node. The operational amplifier controls the second active device according to the output voltage and a core power voltage of a core power line to cause the output voltage to stabilize at a target voltage value. The protection circuit is connected to the input and output power lines, the connecting node and a control node of the first active device, and controls a voltage of the connecting node and the control node of the first active device according to the input and output voltages.


Patent
MStar Semiconductor Inc. | Date: 2016-06-06

A mismatch compensating device includes: a signal generator, synchronously outputting first and second signal; a gain and phase compensator, processing the first and second signals according to a gain parameter and a phase parameter to generate compensated first and second signals; a DAC, performing a digital-to-analog conversion on the compensated first and second signals to generate first and second analog signals; an analog front-end circuit, processing the first and second analog signals to output a joint signal; a mismatch detecting circuit, detecting the power of the joint signal to generate a detection result; a frequency-dependent mismatch compensator, compensating at least one of the first and second signals; and a control circuit, setting the gain and phase parameters and a parameter of the frequency-dependent mismatch compensator according to the detection result to compensate frequency-independent gain and phase mismatch and a frequency-dependent mismatch response.


Patent
MStar Semiconductor Inc. | Date: 2016-06-30

A low-voltage differential signaling (LVDS) driving circuit, coupled to a load resistor via a first output end and a second output end, includes: a voltage generating unit, providing a first reference voltage; a first switch, coupled between the voltage generating unit and a first node; a second switch, coupled between the voltage generating unit and a second node; a third switch, coupled between the first node and a third node, the third node having a second reference voltage; a fourth switch, coupled between the second node and the third node; a first resistor, coupled between the first node and the first output end; and a second resistor, coupled between the second node and the second output end. The first resistor and the second resistor are in a series connection with the load resistor.


A control circuit applied to digital visual interface (DVI) includes a detecting circuit and a switching circuit. The detecting circuit detects a state of a predetermined pin of a DVI connector to generate a control signal. The switching circuit selectively connects a first pin and a second pin of the DVI connector to one a storage unit storing first identification data and a storage unit storing second identification data according to the control signal.


A signal processing apparatus includes a memory and an expanding unit. The memory stores a plurality of initial coefficients. The expanding unit maps N initial coefficients among the coefficients to a quantization table, as N reference quantization weights, where N is a positive integer greater than 2. The N reference quantization weights are not aligned in the quantization table. The expanding unit generates the target quantization weight, by interpolation, according to the N reference quantization weights and respective distances between a target quantization weight and the N reference quantization weights in the quantization table.


Patent
MStar Semiconductor Inc. | Date: 2016-01-15

A circuit for accessing a memory is provided. The memory includes a scatter table storage region and a plurality of storage regions. The scatter table storage region stores a plurality of entries that record starting addresses and sizes of the data storage regions, respectively. The circuit includes an accessing circuit and a cache. The cache stores an entry read from the scatter table storage region. When the accessing circuit needs to access data from the data storage regions, the accessing circuit issues a read request to the cache to read the entry from the cache, determines whether the data is stored in the storage region recorded by the entry according to contents of the entry, and further accordingly determines whether to access the memory to obtain the data according to the contents of the entry.


A circuit structure for suppressing electromagnetic interference (EMI) of DDR SDRAM signals, applied to a memory interface unit (MIU) of a DDR SDRAM, includes: a first conducting line, coupled to a reference level; a second conducting line, parallel to the first conducting line, coupled to the reference level; a third conducting line, between and parallel to the first and second conducting lines, transmitting a signal, the first, second and third conducting lines located on a same plane; and a connecting component, having two ends, one of the two ends electrically connected to the first conducting line and the other of the two ends electrically connected to the second conducting line, the connecting component crossing and electrically insulated from the third conducting line.


Patent
MStar Semiconductor Inc. | Date: 2016-03-29

A time de-interleaving circuit applied to a communication system to de-interleave an interleaved signal is provided. The interleaved signal includes a plurality of cells. The time de-interleaving circuit includes a memory module and a buffering memory module. The memory module stores the cells, which are in a unit of a plurality of cells to form a plurality of cell groups. The memory module is accessed in a unit of one cell group. The buffering memory module buffers a part of the cells from the memory module to arrange an output sequence of the cells.


An operating mode distinguishing method, a touch point determining method and a touch control circuit are provided. It is determined whether an underwater mode is entered according to a self capacitance value and a mutual capacitance value. In the underwater mode, a touch point position is determined according to deformation of a substrate.


A method for performing time and cell de-interleaving on an interleaved signal including a plurality of cells is provided. The method includes: providing a first memory for storing the cells, the first memory written and read each time in a unit of one cell group, the cell group including K cells, where K is a positive integer greater than 1; providing a second memory for storing the cells read from the first memory; reading the cells from the first memory, and writing the cells to the second memory according to a writing rule of a plurality of permutation rules, K consecutive cells written to the second memory being from the same cell group; and reading the cells from the second memory according to a reading rule of the permutation rules, to cause the cells read from the second memory to be complete with time de-interleaving and cell de-interleaving.

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