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San Jose, CA, United States

Patent
Monolithic Power Systems Inc. | Date: 2015-02-13

A semiconductor device has: a gate region having a dielectric layer and a conducting layer; an N-type drain region having a lightly doped drift region and a highly doped drain contact region formed in the drift region, wherein the drain region is at a first side of the gate region; a P-type body region adjacent to the drain region, the body region having a lightly doped first portion body region, a second portion body region, and a highly doped body contact region; and an N-type highly doped source region in the body region, wherein the source region is at a second side of the gate region; wherein the first portion body region is doped with boron, the second portion body region is doped with boron and indium in the first portion body region, and the second portion body region is located adjacent to and beneath the source region.


Processes of assembling microelectronic packages with lead frames and/or other suitable substrates are described herein. In one embodiment, a method for fabricating a semiconductor assembly includes forming an attachment area and a non- attachment area on a lead finger of a lead frame. The attachment area is more wettable to the solder ball than the non-attachment area during reflow. The method also includes contacting a solder ball carried by a semiconductor die with the attachment area of the lead finger, reflowing the solder ball while the solder ball is in contact with the attachment area of the lead finger, and controllably collapsing the solder ball to establish an electrical connection between the semiconductor die and the lead finger of the lead frame.


A method having a negative output voltage at a negative output terminal of a charge pump tracking a positive output voltage at a positive output terminal of the charge pump. The charge pump comprises a plurality of switches and each of the plurality of switches has a serially coupled resistance. The method comprises selecting the serially coupled resistance for at least one of the plurality of switches to be different to each of the other respective serially coupled resistances associated to the other switches.


Patent
Monolithic Power Systems Inc. | Date: 2014-05-29

A field effect transistor (FET), a termination structure and associated method for manufacturing. The FET has a plurality of active transistor cells and a termination structure. The termination structure for the FET includes a plurality of termination cells arranged substantially in parallel from an inner side toward an outer side of a termination area of the FET. Each of the termination cells comprises a termination trench lined with a termination insulation layer and filled with a termination conduction layer. The innermost termination cell is electrically coupled to gate regions of the active transistor cells while the rest of the termination cells are electrically floating.


Patent
Monolithic Power Systems Inc. | Date: 2015-08-19

A design server provides an online service for remotely configuring a voltage regulator integrated circuit (IC). A customer may employ a customer computing device to connect to the design server. The design server may receive from the customer computing device a user requirement for the voltage regulator IC. The design server may select one or more external components to configure the voltage regular IC to meet the user requirement. The design server may automatically place an order for the external components online. The external components may be available from commercial partners of the vendor of the voltage regulator IC.

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