Imran M.,MJCET |
Sayeed Ahmed G.M.,Alagappa Chettiar College of Engineering And Technology
Materials Today: Proceedings | Year: 2015
This Research paper studies about the designing and simulation aspects of automatic arc welding system using digital control with the help of Proteus Simulation software. The welding sequence considered for the study consists of five intervals they are Standby, Squeeze, Weld, Hold, and Release intervals. A separate stepping interval circuit with a decoder to step the intervals from one to another is designed and analysis is done using a decoding technique. The designed stepping circuit ensures the correct order of the five intervals of the welding system, also a separate stepping of heat-cool sub intervals of weld interval is also designed with a user defined preset time counter circuit so that welding interval can be timed based on the user defined priority and can also be stepped between the two heat and cool sub intervals based on the total time assigned by the user. The digital automatic control system is developed to accurately control the arc welding system for welding of two given metal pieces. This report concerns automatic welding system with digital control and is directed to the improvement of certain drive and guide means for a relatively freely carried welding of wheel rim and wheel spider for continuous welding of a part resting on a freely rotatable table. The drive and guide means are carried on the welding head and impart drive to the part while maintaining the welding head properly positioned relative to the part. The system presented is a slightly simplified version of a real automobile wheel-welding system. Although system operation is explained in terms of wheel welding, the design of the system has much in common with other welding operations utilizing the basic industrial automatic welding sequence of Squeeze, Weld, Hold, Release, and Standby with digital control. © 2015 Elsevier Ltd.
Mastanaiah P.,Toshiba Corporation |
Basha S.K.,M.J.C.E.T. |
Materials Today: Proceedings | Year: 2015
Long life and reliable operation are key requirements of any electronic system. Excessive heat dissipation in components can cause them to degrade or fail soon than would normally be expected. this report deals with an electronic component called low voltage inverter, total heat dissipation of the unit is 420 w.}the heat transfer coefficient is calculated for natural convection using free convection simplified expression for air at atmospheric pressure. Thermal analyses have been done to predict the temperature profile in the electronic component using ANSYS. From the thermal mapping temperatures obtained are larger than the safe limit. The safe junction temperature for mosfet is 165 °c actual temperatures are around 1000°c for natural convection. Therefore thermally, the system fails if cooling is done through natural convection then the unit is redesigned for forced convection cooling thereby providing airflow path. The heat transfer coefficient is calculated using correlations for in line arrays for heated components. The thermal analysis has been made to predict the temperature profile in the mosfets using ANSYS. For mass flow rate of 8g/sand 1og/s, the junction temperature profiles have been calculated and found to be 141°c. Therefore optimum mass flow rate have been found to be 8g/sec, the unit was developed and also tested experimentally for different mass flow rate, for which same 8g/s of air is found optimum at ground testing center unit was set to function for which maximum junction temperature was less than the theoretical value by few units and hence unit is checked for its validity. © 2015.
Yarlagadda V.,VNR VJIET |
Sankar Ram B.V.,JNTUH College of Engineering |
Communications in Computer and Information Science | Year: 2013
The design, Fabrication of 4-Kvar 3-phase fixed capacitor-thyristor controlled reactor (FC-TCR) type SVC has been developed in the laboratory for a Single Machine Single Bus (SMSB) Test System. The test system is setup in the laboratory to evaluate the FC-TCR type SVC in stabilizing bus voltage. It comprises of a 3-phase Synchronous Machine of 5kva capacity and a 3-phase squirrel cage Induction Motor of 5HP Rating. 3-Ph SVC have been designed and fabricated and tested by connecting it to a SMSB Test System and experimental results have been presented in this paper. The Power - Voltage (P-V) and Power - Load angle (P-δ) Curves of the SMSB Test system with and without SVC have been plotted which shows the effectiveness of SVC on Generator and Voltage Stability enhancement. © 2013 Springer-Verlag.
Asrar Ahmed M.,MJCET |
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) | Year: 2013
The Integration of MANETs and infrastructure networks such as Internet, extends network coverage and increases the application domain of MANET. Several strategies exist for integration of two networks. Most of them presume that a non-adversarial environment prevails in the network. However such an ideal scenario is not always guaranteed. Nodes many behave maliciously due to scarcity of resources, congestion, or malicious intentions. In this paper a trust based, load aware, and secure gateway discovery for IIM is proposed. It employs the concept of mutual trust and authentication among nodes to prevent malicious activities. However a notable exception is that a node may experience packet-drop due to congestion on route or overflow in the interface queue of an intermediate node; this is not a malicious behaviour. In order to avoid such false malicious behaviours, we employ an effective and adaptive load balancing scheme to avoid congested routes. Thus it would be a novel strategy that ensures the routing in the Integrated Internet and MANET to be trustworthy, secure, efficient, and robust. © 2013 Springer-Verlag Berlin Heidelberg.
Qadeer S.,MJCET |
Ali Khan M.Z.,IITH
2011 International Conference on Multimedia, Signal Processing and Communication Technologies, IMPACT 2011 | Year: 2011
In this paper the analysis of overall quantization loss for the Radix-4 and Radix-8 Fast Fourier Transform (FFT) algorithms is extended to the case where the twiddle factor word length is different from the register word length. Simulation results, that validate the theoretical analysis, are then presented. © 2011 IEEE.
Pasha M.,MJCET |
Farooq M.U.,MJCET |
Khan K.-U.-R.,ACE Inc
Advances in Intelligent Systems and Computing | Year: 2016
Vehicular cloud computing (VCC) adapts from the fact that vehicular nodes can use their on-board computational power, storage, and communication resources to interact with the Cyber-Physical elements. Through this study we identify VCC as an essential stepping stone toward visualizing the Internet of Vehicles (IoV) ecosystem to integrate mobile ad hoc networks, wireless sensor networks, mobile computing, and cloud computing. We provide a classification on the state of the art of VCC by drawing a relationship between the existing domains and IoV through a review of the important works carried recently in the literature. Finally, we present a proof of concept model for vehicular clouds and propose a vehicular resource discovery protocol and evaluate it through simulations using OMNeT++ and SUMo. © Springer Science+Business Media Singapore 2016.
Imran M.,MJCET |
Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics | Year: 2015
Semiconductors have many applications in industry environment. In power systems they are used as switching devices. This paper concentrates on one of the widely used switching device Thyristor and its application for the analysis of Thyristor Controlled Reactor- TCR as a reactive power compensator. The TCR circuit will be investigated by carrying out theoretical mathematical analysis, software simulation and practical work. The results will be compared and discussed and conclusions will be delivered. © 2015 IEEE.
Siddiqua A.,MJCET |
Sridevi K.,MJCET |
Mohammed A.A.K.,Innovative Technologies
International Conference on Signal Processing and Communication Engineering Systems - Proceedings of SPACES 2015, in Association with IEEE | Year: 2015
Mobile ad hoc networks (MANETs) are a collection of mobile hosts which communicate with each other with no central network authority or fixed infrastructure. Due to its characteristics like mobility and heterogeneity ad hoc networks are more vulnerable to attacks. Black hole is an attack where all the packets forwarded to attacker node, by neighboring nodes, are dropped intentionally. In this paper, we propose a secure knowledge algorithm which aims to detect and prevent the black hole by considering the packet drop reasons in promiscuous mode. Existing AODV routing protocol is modified to detect and prevent the black hole attack The experiment results show that our proposed algorithm secure the AODV against black hole attack in MANETs. © 2015 IEEE.
Ali Khan M.S.,M.J.C.E.T. |
Suresh A.,Sreyas Institute of Engineering and Technology |
Journal of Engineering, Design and Technology | Year: 2016
Purpose – The purpose of this paper is to evaluate the performance of the semi-active fluid damper. It is recognized that the performance of such a damper depends upon the magnetic and hydraulic circuit design. These dampers are generally used to control the vibrations in various applications in machine tools and robots. The present paper deals with the design of magneto-rheological (MR) damper. A finite element model is built to analyze and understand the performance of a 2D axi-symmetric MR damper. Various configurations of damper with modified piston ends are investigated. The input current to the coil and the piston velocity are varied to evaluate the resulting change in magnetic flux density (B), magnetic field (H), field dependent yield stress and magnetic force vectors. The simulation results of the various configurations of damper show that higher magnetic force is associated with plain piston ends. The performance of filleted piston ends is superior to that of other configurations for the same magnitude of coil current and piston velocity. Design/methodology/approach – The damper design is done based on the fact that mechanical energy required for yielding of MR fluid increases with increase in applied magnetic field intensity. In the presence of magnetic field, the MR fluid follows Bingham’s plastic flow model, given by the equation τ = η γ•+τ y (H) τ>τ y . The above equation is used to design a device which works on the basis of MR fluid. The total pressure drop in the damper is evaluated by summing the viscous component and yield stress component which is approximated as ΔP = 12ηQL/g3W + CτyL/g, where the value of the parameter, C ranges from a minimum of 2 (for ΔPτ ΔPη less than approximately 1) to a maximum of 3 (for ΔPτ/ΔPη greater than approximately 100). To calculate the change in pressure on either side of the piston within the cylinder, yield stress is required which is obtained from the graph of yield stress vs magnetic field intensity provided by Lord Corporation for MR fluid −132 DG. Findings – In this work, three different finite element models of MR damper piston are analyzed. The regression equations, contour plots and surface plots are obtained for different parameters. This study can be used as a reference for selecting the parameters for meeting different requirements. It is observed from the simulation of these models that the plain ends model gave optimum magnetic force and 2D flux lines with respect to damper input current. This is due to the fact that the plain ends model has more area when compared with that of other models. It is also observed that filleted ends model gave optimum magnetic flux density and yield stress. As there is reduced pole length in the filleted ends model, the MR fluid occupies vacant area, and hence results in increased flux density and yield shear stress. The filleted ends assist the formation of dense magnetic flux lines thereby increasing the flux density and yield stress. This implies that higher load can be carried by the filleted ends damper even with a smaller size. Originality/value – This work is carried out to manufacture different capacities of the dampers. This can be applied as vibration controls. © 2016, © Emerald Group Publishing Limited.
Lakshmi G.S.,GCET |
Fatima D.,MJCET |
Madhavi B.K.,Sridevi Womens College
Proceedings of the 3rd International Conference on Devices, Circuits and Systems, ICDCS 2016 | Year: 2016
Reversible logic gates became very important and computing paradigm having its applications in low power CMOS technologies and Quantum computing . Reversible logics are used to reduce the depth of the circuits . This paper introduces a new architecture of 4:2 Compressor based Vedic 8×8 bit Multiplier using reversible logic and is compared with conventional multipliers using Reversible logic and it was observed that the parameters like Hardware Complexity, power and Delay are improved over other Reversible multipliers. The design is simulated, synthesized and power estimation was done using TSMC 180nm technology using Cadence Digital tools. © 2016 IEEE.