FET MITS

Rajasthan, India
Rajasthan, India
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Sharma K.G.,FET MITS | Sharma T.,FET MITS | Singh B.P.,FET MITS | Arora N.,FET MITS
AIP Conference Proceedings | Year: 2010

The length of interconnect and number of repeaters increases with increasing complexity of the VLSI chip. The power delay product and frequency of operation plays significant role in designing of repeater. Earlier proposed low-voltage swapped-body (LVSB) bias buffer [4] design shows better performance than the earlier conventional No-Body-Bias (NBB) buffer. Sub-threshold grounded-body (STGB) bias buffer design [1] proves even better than the LVSB buffer design in sub-threshold region for medium frequency applications as per the simulation results at 180 nm - 90nm technologies. © 2010 American Institute of Physics.


Sharma T.,FET MITS | Sharma K.G.,FET MITS | Singh B.P.,FET MITS | Arora N.,FET MITS
AIP Conference Proceedings | Year: 2010

This paper proposes a new design of 3T XOR gate. The proposed design of XOR gate is superior in terms of the speed, power consumption and power-delay product in comparison to other 3T XOR gate designs available in the literature. The simulation has been carried out on Tanner EDA tool on BSIM3v3 90nm technology. © 2010 American Institute of Physics.


Sharma T.,FET MITS | Sharma K.G.,FET MITS | Singh B.P.,FET MITS
TechSym 2010 - Proceedings of the 2010 IEEE Students' Technology Symposium | Year: 2010

Full adder is an essential component for the design and development of all types of processors viz. digital signal processors (DSP), microprocessors etc. Adders are the core element of complex arithmetic operations like addition, multiplication, division, exponentiation etc. In most of these systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is a significant goal. The present study proposes an energy efficient full adder cell with least MOS transistor count that reduces the serious problem of threshold loss. It considerably increases the speed. Result shows 45% improvement in threshold loss problem, 40% improvement in power-delay product over the other types of adders with comparable performance. The simulation has been carried out on Tanner EDA tool on BSIM3v3 90nm and 130nm technologies. © 2010 IEEE.


Sharma K.G.,FET MITS | Sharma T.,FET MITS | Singh B.P.,FET MITS | Sharma M.,FET MITS
2011 International Conference on Devices and Communications, ICDeCom 2011 - Proceedings | Year: 2011

Low power device design is now a vital field of research due to increase in demand of portable devices. This research paper proposes the modified Single Edge Triggered (SET) D-flip flop design for the portable applications. Design is tested for various substrate bias voltages in sub-threshold region to opt for better design. Design comparison between previously reported design and modified design is performed at 65nm and 45nm to show technology independence. Comparative simulation results show that area and power efficient SET D-FF design is better choice for portable applications. © 2011 IEEE.

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