Time filter

Source Type

Zürich, Switzerland

Silay K.M.,Ecole Polytechnique Federale de Lausanne | Silay K.M.,Miromico AG | Dehollain C.,Ecole Polytechnique Federale de Lausanne | Declercq M.,Ecole Polytechnique Federale de Lausanne
IEEE Sensors Journal | Year: 2013

This paper presents a closed-loop remote powering link for wireless cortical implants. The link operates from a single power supply at the external reader and delivers power to the implant adaptively under changing load conditions. A feedback information is sent from the implant to the external reader about the power consumption in the implant and the external reader adapts the amount of transmitted power depending on this feedback. In addition, an in vitro measurement setup is fabricated in order to characterize the performance of the wireless energy transfer when the implant is immersed into saline solution. The implant is packaged by using biocompatible materials and the operation of the remote powering link is demonstrated in air and in vitro for a wide range of load power delivered from the voltage regulator. The power transfer efficiency of the overall closed-loop remote powering link is measured to be 10.6% in vitro at nominal load power of 10 mW. Finally, the operation of the implant in vitro is demonstrated over a five-week period. © 2001-2012 IEEE. Source

Reutemann R.,Miromico AG | Ruegg M.,Miromico AG | Keyser F.,IBM | Bergkvist J.,IBM | And 3 more authors.
IEEE Journal of Solid-State Circuits | Year: 2010

This paper describes the design of a product-level low-power source-synchronous link receiver macro for data rates of 3.26.4 Gb/s. The receiver macro consists of 22 data channels plus one forwarded-clock channel, and supports both differential and ground termination. A pulsed CDR with programmable bandwidth is implemented to save power in the CDR. Time dithering is applied to the CDR to avoid notches in the jitter tolerance curve. The receiver clock path incorporates both a clean-up PLL and a polyphase filter for RX clock generation, from which one can be chosen to generate the receive clock. It is shown how jitter in a source-synchronous link is related to skew between clock and data, as well as cross-talk from the data to the clock wires. The jitter performance of the RX using either the polyphase filter or the PLL for clock generation is compared for different loop bandwidths. The RX core was implemented in a 65 nm Bulk CMOS technology. Total power consumption for the 22+1 lane RX PHY core running at 6.4 Gbps with the polyphase filter and in pulsed CDR mode is 635 mW or 4.5 mW/Gbps. © 2006 IEEE. Source

Bulzacchelli J.F.,IBM | Menolfi C.,IBM | Beukema T.J.,IBM | Storaska D.W.,IBM | And 22 more authors.
IEEE Journal of Solid-State Circuits | Year: 2012

This paper presents a 28-Gb/s transceiver in 32-nm SOI CMOS technology for chip-to-chip communications over high-loss electrical channels such as backplanes. The equalization needed for such applications is provided by a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter and a two-stage peaking amplifier and 15-tap decision-feedback equalizer (DFE) in the receiver. The transmitter employs a source-series terminated (SST) driver topology which doubles the speed of existing half-rate designs. The high-frequency boost provided by the peaking amplifier is enhanced by adopting a structure with capacitively coupled parallel input stages and active feedback. A capacitive level-shifting technique is introduced in the half-rate DFE which allows a single current-integrating summer to drive the four parallel paths used for speculating the first two DFE taps. Error-free signaling at 28 Gb/s is demonstrated with the transceiver over a channel with 35 dB loss at half-baud frequency. In a four-port core configuration, the power consumption at 28∼Gb/s is 693 mW/lane. © 2012 IEEE. Source

Gangasani G.R.,IBM | Hsu C.-M.,IBM | Bulzacchelli J.F.,IBM | Beukema T.,IBM | And 16 more authors.
IEEE Journal of Solid-State Circuits | Year: 2014

This paper describes key design features of a 32 Gb/s 4-tap FFE/15-tap DFE transceiver in 32 nm SOI CMOS which mitigate major sources of degradation in transceiver performance. The transceiver employs a passive feed-forward restore (FFR) scheme in an on-chip AC-coupling network to prevent pattern-dependent baseline wander, a low-latency clock and data recovery (CDR) to improve high-frequency jitter tolerance, and a token-based power management scheme to reduce supply ripple. At 32 Gb/s, the transceiver can equalize a channel with 30 dB of loss at a bit-error rate below 10-12 while consuming 21 mW/Gbps at 1 V supply and an area of 0.7 mm2. © 1966-2012 IEEE. Source

Toifl T.,IBM | Menolfi C.,IBM | Ruegg M.,Miromico AG | Reutemann R.,Miromico AG | And 9 more authors.
IEEE Journal of Solid-State Circuits | Year: 2012

A low-power receiver circuit in 32 nm SOI CMOS is presented, which is intended to be used in a source-synchronous link configuration. The design of the receiver was optimized for power owing to the assumption that a link protocol enables a periodic calibration during which the circuit does not have to deliver valid data. In addition, it is shown that the transceiver power and the effect of high-frequency transmit jitter can be reduced by implementing a linear equalizer only on the receive side and avoiding a transmit feed-forward equalizer (TX-FFE). On the circuit level, the receiver uses a switched-capacitor (SC) approach for the implementation of an 8-tap decision-feedback equalizer (DFE). The SC-DFE improves the timing margin relative to previous DFE implementations with current feedback, and leads to a digital-style circuit implementation with compact layout. The receiver was measured at data rates up to 13.5 Gb/s, where error free operation was verified with a PRBS-31 sequence and a channel with 32 dB attenuation at Nyquist. With the clock generation circuits amortized over eight lanes, the receiver circuit consumes 2.6 mW/Gbps from a 1.1 V supply while running at 12.5 Gb/s. © 2012 IEEE. Source

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