Grenoble, France


Grenoble, France
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Dimakos A.,University Grenoble Alpes | Dimakos A.,CEA Grenoble | Stratigopoulos H.-G.,Paris-Sorbonne University | Siligaris A.,MINATEC Campus | And 3 more authors.
Journal of Electronic Testing: Theory and Applications (JETTA) | Year: 2015

Testing the RF functions of systems-on-chip incurs a very high cost. Built-in test is a promising alternative to facilitate testing and reduce cost. However, designing built-in test circuits that tap into the sensitive RF signal paths, in order to extract useful information for the purpose of testing, often finds the designers reluctant since it results in some performance degradation that needs to be accounted for during the design. In this paper, we study a transparent built-in test approach based on non-intrusive sensors that are not electrically connected to the RF circuit under test. The non-intrusive sensors simply monitor process variations and by virtue of this they are capable of tracking variations in the performances of the RF circuit as well. The alternate test paradigm is employed to map the outputs of the sensors to the performances, in order to replace the standard tests for measuring the performances directly. We discuss in this paper the principle of operation of these sensors and we demonstrate the non-intrusive test approach on a 65nm RF low noise amplifier. © 2015 Springer Science+Business Media New York

Kerlain A.,Development and Production Center | Brunner A.,Development and Production Center | Sam-Giao D.,Development and Production Center | Pere-Laperne N.,Development and Production Center | And 4 more authors.
Journal of Electronic Materials | Year: 2016

For high operating temperature applications, variation of noise equivalent differential temperature (NETD or NEDT) with temperature is the most relevant figure of merit. NETD(T) models with and without taking into account systemic 1/f noise contribution are presented and compared to recent developments made on P on N technology at Sofradir and CEA-LETI. We show that for mature middle wave infrared HgCdTe technology, no 1/f noise contribution up to 220 K is measured and the focal plane array operation is only limited by the mean performance value degradation, not by an increase of defects. © 2016 The Minerals, Metals & Materials Society

Piccolboni G.,MINATEC Campus | Parise M.,MINATEC Campus | Molas G.,MINATEC Campus | Levisse A.,MINATEC Campus | And 14 more authors.
2016 IEEE 8th International Memory Workshop, IMW 2016 | Year: 2016

In this paper, we propose the integration of an Al2O3/CuTex based Conductive Bridge RAM (CBRAM) device in vertical configuration. The performances of the memory devices are evaluated. 20ns switching time, up to 106 cycles and stable 150°C retention were demonstrated. Functionality is compared with Vertical RRAM integrating an HfO2/Ti OXRAM stack, showing the pros and cons of each configuration. Then 2 potential applications are discussed using design approach. For high density, the Vertical RRAM cell features and circuit are dimensioned to optimize the memory page density. Finally, for neuromorphic applications, selector and array configuration are tuned to reduce the variability in terms of voltage seen by each cell constituting a vertical synapse. © 2016 IEEE.

Lacord J.,MINATEC Campus | Martinie S.,MINATEC Campus | Rozeau O.,MINATEC Campus | Jaud M.-A.,MINATEC Campus | And 2 more authors.
IEEE Transactions on Electron Devices | Year: 2016

In this paper, we propose an analytical model to accurately evaluate the parasitic capacitances of an advanced 7-nm-node multigate device structure: 1) FinFET on Silicon On Insulator (SOI) (FFSOI) and 2) stacked nanowire on SOI (SNWSOI). Our model, validated through 3-D TCAD simulations, accounts for gate contact, advanced process bricks, such as gate last, BAR contact, and low-k spacer, but also multilayer dielectric by introducing an equivalent permittivity. Finally, FFSOI and SNWSOI architectures are compared from this parasitic capacitance point of view. © 2015 IEEE.

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