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Boise, ID, United States

Micron Technology, Inc. is an American multinational corporation based in Boise, Idaho, best known for producing many forms of semiconductor devices. This includes DRAM, SDRAM, flash memory, and SSDs. Its consumer products are marketed under the brands Crucial Technology and Lexar. Micron and Intel together created IM Flash Technologies, which produces NAND flash memory. Micron was named one of Thomson Reuters top 100 global innovators in 2012 and 2013. Micron Technology is also ranked among the Top 5 Semiconductor producing companies in the world. As of January 2015, its market capitalization was $32 billion. Wikipedia.


Grant
Agency: Cordis | Branch: H2020 | Program: CSA | Phase: ICT-25-2015 | Award Amount: 1.16M | Year: 2016

Understanding properties of nanoparticles (and in general of nano-functionalized materials) and how they behave in living systems is a relatively new area of scientific study. The scientific community has not yet been able to derive harmful properties of nanomaterials from the properties of the bulk material. So a precautionary approach is required when handling and using these materials in circumstances where exposure to nanomaterials cannot be excluded. The purpose of this project is to promote good practices (i.e. by following up standards), identify gaps in methodologies and direction for further investigations in order to support risk assessment in order to protect human health. The project also aims to initiate communication with stakeholders to support informed decision making and governance of risks related to handling of nanomaterials and medical surveillance of the workforce in the semiconductor fabrication process. We will focus on several use cases. For example, the use of nanomaterials in chemical mechanical polish slurries for semiconductor manufacture is well documented; however there are also other scenarios where nanomaterials may be used or generated (e.g. wafer cleaving, cleaning of rector chambers or exhaust air ducts).


Patent
Micron Technology Inc. | Date: 2016-01-12

A method of forming an array of memory cells includes forming lines of covering material that are elevationally over and along lines of spaced sense line contacts. Longitudinal orientation of the lines of covering material is used in forming lines comprising programmable material and outer electrode material that are between and along the lines of covering material. The covering material is removed over the spaced sense line contacts and the spaced sense line contacts are exposed. Access lines are formed. Sense lines are formed that are electrically coupled to the spaced sense line contacts. The sense lines are angled relative to the lines of spaced sense line contacts and relative to the access lines. Other embodiments, including structure independent of method, are disclosed.


Patent
Micron Technology Inc. | Date: 2016-01-11

Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate.


Patent
Micron Technology Inc. | Date: 2016-01-11

A method of fabricating integrated circuitry includes forming a first conductive line. First elemental tungsten is deposited directly against an elevationally outer surface of the first conductive line selectively relative to any exposed non-conductive material. Dielectric material is formed elevationally over the first conductive line and a via is formed there-through to conductive material of the first conductive line at a location where the first tungsten was deposited. Second elemental tungsten is non-selectively deposited to within the via and electrically couples to the first conductive line. A second conductive line is formed elevationally outward of and electrically coupled to the second tungsten that is within the via.


Patent
Micron Technology Inc. | Date: 2016-01-11

A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.

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