Boise, ID, United States
Boise, ID, United States

Micron Technology, Inc. is an American multinational corporation based in Boise, Idaho, best known for producing many forms of semiconductor devices. This includes DRAM, SDRAM, flash memory, and SSDs. Its consumer products are marketed under the brands Crucial Technology and Lexar. Micron and Intel together created IM Flash Technologies, which produces NAND flash memory. Micron was named one of Thomson Reuters top 100 global innovators in 2012 and 2013. Micron Technology is also ranked among the Top 5 Semiconductor producing companies in the world. As of January 2015, its market capitalization was $32 billion. Wikipedia.


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Patent
Micron Technology Inc. | Date: 2017-01-25

Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non- volatile memory mode. In the DRAM expansion mode, one or more of the memory communication charmels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.


Patent
Micron Technology Inc. | Date: 2017-02-22

The present application concerns a holder system for mounting and aligning a machining unit (30) to a machine (20), preferably to a rotary transfer machine. The holder system comprises a holder (1) with a first part (2) being mountable on a machine (20) or being part of a machine (20) as well as a second part (3) which is releasably coupled to said first part (2) in a defined first position. Said second part (3) is coupled to a third part (4), said third part including third coupling means (7) for coupling said third part (4) with a machining unit (30). Positioning means (5, 6) are located between said second part (3) and said third part (4) to allow moving said third part (4) relative to said second part (3) in at least one spatial direction. Further, the holder system comprises at least one alignment station, said alignment station comprising first coupling means for releasably coupling the second part (3) of the holder (1) to said alignment station in said first defined position and at least one measuring device arranged on said alignment station, said measuring device configured to measure the position of said third part (4) or of a machining unit (30) coupled to said third part (4) relative to the second part (3).


Patent
Micron Technology Inc. | Date: 2017-04-12

Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.


Patent
Micron Technology Inc. | Date: 2016-12-28

Some embodiments include a switching component which includes a selector region between a pair of electrodes. The selector region contains silicon doped with one or more of nitrogen, oxygen, germanium and carbon. Some embodiments include a memory unit which includes a memory cell and a select device electrically coupled to the memory cell. The select device has a selector region between a pair of electrodes. The selector region contains semiconductor doped with one or more of nitrogen, oxygen, germanium and carbon. The select device has current versus voltage characteristics which include snap-back voltage behavior.


Patent
Micron Technology Inc. | Date: 2017-04-05

The present disclosure includes apparatuses and methods for a cache architecture. An example apparatus that includes a cache architecture according to the present disclosure can include an array of memory cells configured to store multiple cache entries per page of memory cells; and sense circuitry configured to determine whether cache data corresponding to a request from a cache controller is located at a location in the array corresponding to the request, and return a response to the cache controller indicating whether cache data is located at the location in the array corresponding to the request.


Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a stack of semiconductor dies and a thermally conductive casing at least partially enclosing the stack of semiconductor dies within an enclosure. A package substrate carries the thermally conductive casing, and an interposer is disposed between the thermally conductive casing and the stack of semiconductor dies. A peripheral portion of the interposer extends laterally beyond the stack of semiconductor dies and is coupled to a plurality of conductive members interposed between the peripheral portion and the package substrate.


Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. The capacitor comprises a dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line.


Patent
Micron Technology Inc. | Date: 2016-08-23

Apparatuses and methods for threshold voltage analysis are described. One or more methods for threshold voltage analysis include storing expected state indicators corresponding to a group of memory cells, applying a first sensing voltage to a selected access line to which the group of memory cells is coupled, sensing whether at least one of the memory cells of the group conducts responsive to the first sensing voltage, determining whether a discharge indicator for the at least one of the memory cells has changed responsive to application of the first sensing voltage, and determining that the first sensing voltage is the threshold voltage for a particular program state of the at least one of the memory cells.


Patent
Micron Technology Inc. | Date: 2016-08-23

Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation.


A method includes calculating a first position encoded pattern based on a first data pattern, and using an automata processor to compare the first position encoded pattern to a second position encoded pattern to identify a second data pattern within the first data pattern.

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