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Leuven, Belgium

Spessot A.,Micron Technology Belgium | Caillat C.,Micron Technology Belgium | Ritzenthaler R.,IMEC | Schram T.,IMEC | Fazan P.,Micron Technology Belgium
IEEE Workshop on Microelectronics and Electron Devices, WMED | Year: 2014

An impact analysis of the various thermal budgets on the electrical trends of a HKMG-Metal Inserted Poly Si gate (MIPS) process through Technology Computer-Aided Design (TCAD) is reported. A good agreement between simulation and experimental data is shown for NMOS and PMOS FETs in a low power and low cost 45 nm technology node. The impact of the C and Ge+C co-implantation on the device performance is explored, with particular emphasis on the effects on the USJ of additional thermal treatments needed by a DRAM compatible periphery. From this understanding, further device tuning can be foreseen, in order to meet specific design requests. An application example of the optimized process simulation is shown, demonstrating the feasibility of different Vth schemes, ranging from low-power to high performance oriented devices. © 2014 IEEE.

Halder S.,IMEC | Stiers K.,IMEC | Miller A.,IMEC | De Wolf I.,IMEC | And 4 more authors.
ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings | Year: 2013

In this paper we discuss the numerous metrology and inspection challenges that need to be overcome to really have high volume manufacturing of 3D integrated chips. The key metrology and inspections issues are addressed module wise. We start with the TSV module then move on to the wafer bonding and thinning module. This is followed by the bumping module, de-bonding module and finally we finish with the stacking module. Within each of the modules we show the possible solutions for metrology and inspection and also discuss limitations of the available metrology and inspection if it is warranted. © 2013 IEEE.

Nazir A.,IMEC | Nazir A.,Catholic University of Leuven | Spessot A.,Micron Technology Belgium | Eyben P.,IMEC | And 5 more authors.
IEEE Transactions on Electron Devices | Year: 2014

In this paper, we illustrate how high-resolution 2-D carrier profiles from scanning spreading resistance microscopy (SSRM) can be used to predict and understand device performance of dynamic random access memory peripheral transistors with high-k metal gate and ultrashallow junctions. In an earlier study on high-speed complementary metal-oxide-semiconductor logic, the 2-D carrier profiles from SSRM were used as the active 2-D dopant profile input to the device simulator as they are virtually identical. The extensive mobile carrier diffusion caused by the lower concentrations, however, implies a strong difference between the mobile carrier distribution and the dopant distribution such that the same approach is no longer valid. Ideally one would have to generate, based on the carrier profiles, the active dopant distribution through the inverse solution of the Poisson equation (in two dimensions) which is, however, numerically nontrivial and often leads to nonunique results. Therefore, an alternative approach is proposed here, whereby we fine-tune the process simulations such that the resulting simulated carrier profiles match the 2-D SSRM profiles. Upon reaching satisfactory agreement, the simulated profiles can be used as input for a device simulator and be used to predict sensitive device parameters such as drain-induced barrier lowering and threshold voltage rolloff. © 2014 IEEE.

Simoen E.,IMEC | Andrade M.G.C.,IMEC | Andrade M.G.C.,University of Sao Paulo | Almeida L.M.,IMEC | And 6 more authors.
Journal of Integrated Circuits and Systems | Year: 2013

The variability of the low-frequency (LF) noise in n-channel MOSFETs fabricated on an Ultra-Thin Buried Oxide (UTBOX) Silicon-on-Insulator (SOI) substrate has been studied and compared with the variability in the threshold voltage and low-field mobility of the same devices. No correlation has been found between the noise magnitude and the DC parameters, suggesting that the traps responsible for the current fluctuations do not affect the latter. A possible explanation is that the LF noise is dominated by Generation-Recombination (GR) centers in the silicon film, which have less impact on the drain current.

Almeida L.M.,University of Sao Paulo | Sasaki K.R.A.,University of Sao Paulo | Caillat C.,Micron Technology Belgium | Aoulaiche M.,IMEC | And 6 more authors.
Solid-State Electronics | Year: 2013

This paper investigates the front and back gate bias influence on current sense margin and retention time in Ultra-Thin Buried Oxide (UTBOX) Fully Depleted Silicon On Insulator (FDSOI) devices used as a FBRAM (floating body random access memory) cell through simulations and experimental results. This work aims to gain insight into the mechanisms involved into FBRAM operation and optimize the front and back gate biases for achieving the best retention time and current sense margin. The writing '1', through BJT effect, and writing '0', by using capacitive coupling, were verified. We demonstrated that, during the holding, the operation mode of the interfaces is an important factor for the best condition for achieving both a higher current sense margin and a longer retention time, which should be with the front gate in accumulation mode and the back gate in depletion mode. It was also observed that depending on gate bias applied during the hold operation, there are two mechanisms involved in retention time. For less negative gate voltage the retention time is limited by recombination, whereas for more negative gate voltage the generation mechanisms take place. Moreover, the retention time showed more sensitivity to the back gate voltage than the current sense margin. © 2013 Elsevier Ltd. All rights reserved.

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