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Calabrese M.,Olivetti | Miccoli C.,Polytechnic of Milan | Compagnoni C.M.,Polytechnic of Milan | Chiavarone L.,Olivetti | And 8 more authors.
ICICDT 2013 - International Conference on IC Design and Technology, Proceedings | Year: 2013

This work is focused on the accelerated testing of Flash memory reliability, taking our 45 nm NOR technology as a case study to highlight some major issues that may affect the investigation of modern nanoscale devices. In particular, results will be shown on cycling-induced threshold-voltage instabilities coming from charge trapping/detrapping in the cell tunnel oxide during post-cycling data retention or bake experiments, whose characterization relies on the possibility to reduce the experimental time by an increase of the test temperature according to an Arrhenius law via an activation energy EA. These accelerated characterization schemes come from a detailed physical understanding and modeling of the damage creation/recovery dynamics and rely on the careful evaluation of EA. As shown in the case of the investigated NOR technology, this often does not represent a trivial task, due to the large number of spurious effects affecting the threshold voltage of nanoscale memory cells. © 2013 IEEE.


Visalli G.,Micron Semiconductor Italy
Journal of Low Power Electronics | Year: 2012

This paper introduces the best architecture for a novel low-power encoding system suitable for high bandwidth off-chip data buses. The technique, known as Bus Switch, reorders dynamically the lines of a bus in agreement to a permutation scheme such to minimize the total bus switching activity, responsible for the consumption of dynamic energy. The idea was to reduce the area, power and latency of the permutation circuits usin Ing fixed-scheme scrambling units. Moreover, I replaced the toggle count calculation and evaluation circuits with a hierarchical arrangement of analog comparators, representing the bus toggle binary string as a voltage value. I designed the Bus Switch encoder and decoder in semiconductor technologies at 90, 65 and 45 nanometers. The results confirmed that the proposed Bus Switch minimized the required transistors number and the related area and energy consumptions, extending the Bus Switch's field of application. Copyright © 2012 American Scientific Publishers All rights reserved.


Polignano M.L.,Micron Semiconductor Italy | Codegoni D.,Micron Semiconductor Italy | Delcastello G.,Micron Semiconductor Italy | Del Vitto A.,Micron Semiconductor Italy | And 2 more authors.
ECS Journal of Solid State Science and Technology | Year: 2013

In this paper tellurium is characterized as a silicon contaminant. Tellurium is confirmed to be a very slow diffuser, with diffusivity comparable to that of shallow dopants. For this reason, tellurium cannot be revealed by SPV measurements. On the other hand, tellurium acts as an n-type dopant, so tellurium contamination can be revealed by C-V measurements. In addition, tellurium is responsible for the formation of a positive charge at the oxide-silicon interface, and for interface states. Tellurium is also effective in degrading the generation lifetime. DLTS measurements confirmed that tellurium is responsible for two deep levels acting as electron traps. Finally, ToF-SIMS measurements proved to be able to reveal tellurium contamination at the oxide-silicon interface. © 2012 The Electrochemical Society.

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