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Agency: Cordis | Branch: FP7 | Program: CP | Phase: ICT-2007.3.1 | Award Amount: 20.81M | Year: 2008

The project aims at the development of the technology for very high density Non Volatile Memories for mass storage applications down to the 2X nm technology node. The field is receiving increasing attention, due to the explosion of portable multimedia applications, and is forecasted to exceed 40 Billion US$ total available market by 2010. The dominant technology for this application is the floating gate NAND memory. However severe technological roadblocks (reduction in storage charge and electrostatic interference among neighboring cells) are limiting further scaling beyond the 32 nm node. Charge trapping in dielectric layers seems to be a viable alternative to floating gate. The main challenge is the integration of the different new materials, like tunnel dielectric, trapping layer, top dielectric, metal gate at the target technology node and the achievement of an acceptable trade-off between functionality and reliability (e.g. charge retention and endurance). The project will cover material development, cell architecture, modeling of material properties, trapping and conduction behavior in the dielectrics, metal gate materials. Initial studies could be performed on available technology 65-45nm (more relaxed for Universities and research centers) to arrive to full process integration and realization of full arrays in a technology in the 28-36 nm range (the best achievable with available lithography) by two major European semiconductor manufacturers. It will include memory characterization and reliability testing, with the additional aim of defining standards and procedures for reliability assessment. Technology options for higher integration densities, for a given lithography node, will be investigated with the help of public research partners. The final demonstrator will be a fully working memory array in the multi-gigabit range.

Agency: Cordis | Branch: FP7 | Program: CP | Phase: ICT-2009.3.1 | Award Amount: 14.06M | Year: 2010

SEAL is a project for an integrated project consisting of 17 equipment assessment sub-projects in the area of semiconductor manufacturing equipment. The assessment themes are equally spread amongst processing and metrology equipment, heading beyond the current state-of-the-art both for More Moore and More than Moore applications. The strategic objective of SEAL is to effectively combine efforts, resources and expertise in the joint assessment of novel equipment supported by cross-cut R&D dedicated to the identified needs of the assessment sub-projects.For Lithography, the key areas of illumination systems for mask aligners, EUV mask manufacturing and intelligent overlay management are addressed as well as massively parallel e-beam lithography. In addition, three important processes are addressed: low temperature oxidation, cleaning of sensitive interconnect stacks/structures and ion implantation for ultra shallow junctions and defect engineering. For metrology and analysis, the main focus is on enabling innovative systems to efficiently contribute to at-line and in-line monitoring and control within semiconductor facilities. Without such equipment, it will not be possible to validate progressively advanced processes during development and manufacturing.Cross-cut R&D activities relating to all equipment assessment sub-projects are covered including APC, model based control, equipment simulation, enhanced wafer and equipment logistics, advanced communication and man machine-interfaces, and virtual equipment engineering. A common approach for the assessment activities will be utilised with specifications that will be refined for each equipment type for the progressively emerging technology nodes.Overall, SEAL will strengthen the European equipment manufacturing industry in an ideal and sustainable way by combining advanced R&D topics in equipment sub-projects involving a wide community of users, research institutes and equipment suppliers with many SMEs.

Agency: Cordis | Branch: FP7 | Program: CP | Phase: ICT-2007.3.1 | Award Amount: 3.21M | Year: 2008

Today advanced System-in-Package(SiP) can integrate several Large-Scale-Integration(LSI) technologies and functionalities (advanced System-on-Chip-SoC),high-density memories,high-performance analogue-block.Its become strategic to analize and detect potential signal and power integrity failures before the prototype phase.The key to success is a set of integrated EDA tools and modelling flows that combine the availability of accurate models, either extracted by simulations or measurements, with reliable time-domain and system-level verification simulation methodologies.The aim is to develop reliable modelling and simulation solutions for SiP design and verification. The modelling activity will be related to measurement analysis for validating the simulation results and making available characterization measurement platforms.The research activities will be:1)Exploring innovative modelling approaches for Integrated-Circuit (IC) buffers, 3D physical structures and IC power rails beyond the current state-of-art;2)Investigating viable simulation and measurement strategies for SiP signal and power integrity analysis.The models and tools developed will be integrated in a unique EDA simulation platform and efforts will also be devoted to merge as more as possible the developed characterization measurement platforms.At the end of the project it is expected that the flows for extracting accurate simulation models will be available, together with a performing integrated EDA platform and a viable signal integrity measurement methodology. The final targets of project include:a)demonstration of the innovative IC simulation models developed and their related extraction flows by both simulation and measurement;b)the development of an innovative 3D EM field solver;c)the development of a performing SiP design and verification EDA platform;d)a demonstration of the developed signal integrity measurement techniques

Agency: Cordis | Branch: FP7 | Program: CP-FP | Phase: NMP.2012.2.2-2 | Award Amount: 3.23M | Year: 2012

The SYNAPSE project aims at the metalorganic chemical vapor phase deposition (MOCVD) and study of chalcogenide single material, (core) and double material (core-shell) nanowires (NWs), for innovative multi-level phase change memories (PCM). If Ge-Sb-Te is the most studied material for PCM applications, In-based materials, like In-Sb-Te or In-Ge-Te alloys, are also promising, since they are featured by low reset current and high crystallization temperature, paving the way for performing data storage devices even in the automotive field. At the same time, a great attention is currently devoted to the chance to downscale PCM cells by employing chalcogenide NWs. In SYNAPSE, Ge-based and In-based NWs will be first deposited by MOCVD on different substrates and using different bottom-up approaches, the vapor-liquid-solid (VLS) and the selective area growth (SAG). Single material nanowire (SM-NWs) will be in-situ MOCVD-coated by other phase change chalcogenides, to obtain core-shell nanowires (CS-NWs), both free-standing and buried in template matrix. Different material combinations (Ge-Sb-Te/In-Sb-Te/In-GeTe) will be explored in the realization of the CS-NWs, in order to expand the memory level operational features of the obtainable PCM devices. The NW synthesis will be supported by the development and test of precursors for MOCVD. A detailed study of the NW phase switching behavior (reversible amorphous-crystalline transitions) will be carried out and correlated. Special attention will be devoted to the investigation of electrical and thermal properties of the NWs, their phase formation/crystallization dynamics, size-dependent effects and structural/chemical composition. Experimental work will be supported by theoretical modeling and simulation of both crystallization dynamics and electro-thermal behavior. The SYNAPSE consortium is formed by 7 participants (5 academic/research centers and 2 industries) from Italy (3), France (2), Germany (1) and Ireland (1).

Agency: Cordis | Branch: FP7 | Program: CP | Phase: ICT-2007.3.1 | Award Amount: 5.63M | Year: 2007

For developing complex next-generation chips which include a combination of disparate technologies, the circuit integration exclusively in two dimensions has proved to be a seriously limiting factor. Utilising the third dimension for integration of complex chips is a promising technique for removing the bottlenecks in two-dimensional (2-D) integration. Advantages of third-dimension (3-D) integration are in first order form factor and power dissipation.The proposed project ELITE aims at miniaturization and density increase beyond Moore by means of exhaustive die stacking. It takes as development vehicle an advanced solid state drive which will widely substitute traditional hard disk drives for purpose of mobile and hand-held applications and which is considered as the enabler of the up-coming era of mobile data. The system architecture will include a large amount of non-volatile flash memory, one or more microcontrollers and external analog high-speed interface.One of the main topics of ELITE will be the development of a technology for vertical die stacking and for vertical interconnect. Starting from the expertise and experience of the consortium new technology modifications or alternative technologies will be investigated. Also assembly technology will be investigated considering possible later usage in mass-production with its specific requirements on manufacturability and cost.Conceptual and physical simulations will be deployed for planning and ensuring the system architecture and specifying a demonstrator which will prove the feasibility of the concept. Firmware inside the chip will be used to optimize performance by means of parallel tasks, guaranty highly reliable data access as well as controlling power dissipation.As a final step, generalization of the results which are reached with the solid-state drive vehicle will be generalized in order to be re-used for applications from different technical domains and markets.

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