Ōta-ku, Japan
Ōta-ku, Japan

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Nakai T.,Micron Japan Ltd.
Conference Proceedings from the International Symposium for Testing and Failure Analysis | Year: 2010

Currently many methods are available to obtain a junction profile of semiconductor devices, but the conventional methods have drawbacks, and they could be obstacles for junction profile analysis. This paper introduces an anodic wet etching-based two-dimensional junction profiling method, which is practical, efficient, and reliable for failure analysis and electrical characteristics evaluation. Copyright © 2010 ASM International® All rights reserved.


Tanzawa T.,Micron Japan Ltd.
2014 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014 | Year: 2014

This paper proposes a model to help designers maximize output power in systems that contain a DC energy transducer and a DC-DC multiplier charge pump by identifying initial circuit and device parameter estimates for SPICE simulations. This model also enables designers to use simple equations to estimate the sensitivity of the DC transducer's characteristic parameters, like short circuit current and output impedance, on the charge pump's output power. © 2014 IEEE.


Tanzawa T.,Micron Japan Ltd.
Proceedings - IEEE International Symposium on Circuits and Systems | Year: 2015

This paper proposes an analytical, closed-form multi-sine AC-DC voltage multiplier model and investigates the dependency of input and output power on circuit and device parameters. Comparisons of the proposed model with SPICE simulation results are also provided for validation under various circuit parameters, such as the number of stages and capacitance per stage, and device parameters such as saturation current of diodes. The results suggest a voltage multiplier operating with a continuous wave is not less efficient than one operating with a multi-sine wave. This is in contrast to existing papers that show an entire system which includes both a voltage multiplier and rectenna is more efficient with a multi-sine wave than a continuous wave. © 2015 IEEE.


Tanzawa T.,Micron Japan Ltd.
Proceedings - IEEE International Symposium on Circuits and Systems | Year: 2015

This paper proposes a comprehensive optimization methodology to simultaneously determine the clock frequency, area ratio of pump capacitor to switching circuit, number of stages, and capacitor size of integrated switched-capacitor charge pump voltage multipliers. Power efficiency of the charge pump is also discussed in various views. How the top and bottom plate parasitic capacitance and the threshold voltage of the switching circuit affect power efficiency is reviewed. The optimization methodology is demonstrated. Comparisons of the model with SPICE simulation results are also provided for validation. © 2015 IEEE.


Tanzawa T.,Micron Japan Ltd.
IEEE Transactions on Circuits and Systems II: Express Briefs | Year: 2011

This brief proposes an explicit Dickson charge pump model, including the effect of the resistance of switching devices on the pump performance. Using this model, one can estimate an optimum clock frequency and the size of the transferring transistors in terms of the main pump capacitors, the auxiliary capacitors, and the transfer transistors to maximize the output current under the same silicon area in a given technology. © 2011 IEEE.


Tanzawa T.,Micron Japan Ltd.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems | Year: 2012

This brief discusses modeling of a high-voltage generator, including a charge pump circuit and a regulator for accelerating system-level simulations. Event-driven simulators become slow when hard switching frequently occurs to enable charge pump circuits even with a conventional model. A current mirror is added to the pump model and is connected to an output node of a comparator in the voltage detector to make every node in the feedback loop fully analog. Simulation results show that the simulation time for voltage generators' system is reduced by a factor of about 10 with an error of 5% in comparison with the conventional model. © 1993-2012 IEEE.


Sakui K.,Micron Japan Ltd
IEEE Solid-State Circuits Magazine | Year: 2013

The main feature of Flash Memory is that it can retain data when the power is shut down, which is an indispensable part of a modern electronic system. System designers benefited greatly when the electrically erased and programmed nonvolatile Flash Memory became available. DRAM has been mainly used for the main memory to store the data and program in the computer. DRAM is fast, however, it can no longer retain data when the power is shut down. It is called a volatile memory. Therefore, personal computers have external storage devices of Hard Disk Drive (HDD) at any cost. This replacement of HDD by Flash Memory has been just got started. Flash Memory has a variety of advantages; low cost, light, low power (eco-friendly), vibration free, and resistant to moisture, etc. These good points of Flash Memory have innovatively produced a digital camera, cellular phone, and removal storage card. And now, Solid State Disk (SSD) has been fed directly into a computer in the replacement of HDD. © 2009-2012 IEEE.


Tanzawa T.,Micron Japan Ltd.
2014 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014 | Year: 2014

This paper proposes an analytical, closed-form AC-DC voltage multiplier model and investigates the dependency of output current and input power on circuit and device parameters. The model uses no fitting parameters and a frequency term applicable to both multipliers using diodes and metal-oxide semiconductor field effect transistors (MOSFETs). Analysis enables circuit designers to estimate circuit parameters, such as the number of stages and capacitance per stages, and device parameters such as saturation current (in the case of diodes) or transconductance (in the case of MOSFETs). Comparisons of the proposed model with SPICE simulation results as well as other models are also provided for validation. © 2014 IEEE.


Tanzawa T.,Micron Japan Ltd.
IEEE Transactions on Circuits and Systems I: Regular Papers | Year: 2010

This paper compares the performance among two-phase switched-capacitor multipliers to identify the optimum topology with the smallest circuit area. The optimum number of stages is calculated for every multiplier to minimize the circuit area under the condition that a certain current is outputted with a given output voltage. Then, the circuit areas of the serialparallel, linear (LIN), Fibonacci, and 2N multipliers are compared. Results show that the LIN cell is the best for integration because of the smallest total capacitor area and the highest current efficiency under the assumption that the parasitic capacitance is not smaller than 10% of the multiplier capacitance, and the Fibonacci cell is the best for discrete application because of the minimum number of capacitor components with moderate current efficiency under the assumption that the parasitic capacitance is not larger than 1% of the multiplier capacitance. © 2010 IEEE.


Tanzawa T.,Micron Japan Ltd.
IEEE Transactions on Power Electronics | Year: 2014

This letter expands upon an optimum design of integrated switched-capacitor Dickson charge pump multipliers for minimizing the power, which considers the parasitic capacitance of both the top and bottom plates of pump capacitors. This letter also discusses an optimum design with area power balance, and suggests that the number of stages should be ε NMIN, where is 1.5-1.7 and NMIN is the minimum number of stages required to meet the condition that the output current is zero at a given output voltage. © 1986-2012 IEEE.

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