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Agrate Brianza, Italy

Mauri A.,Micron | Amoroso S.M.,Polytechnic of Milan | Monzio Compagnoni C.,Polytechnic of Milan | MacOni A.,Polytechnic of Milan | And 2 more authors.
Solid-State Electronics

This paper presents a comprehensive numerical modeling for the threshold-voltage transients of nitride-based memory devices during programming, erasing and data retention. The developed numerical tool self-consistently solves the Poisson, continuity and trapping equations in the nitride layer using a drift-diffusion formalism. The continuity equation has been discretized using the Scharfetter-Gummel scheme and a modified Gummel-map has been optimized to ensure fully convergence of the equations. The numerical model is able to describe the memory device operation for different gate bias regimes, therefore addressing both the program/erase and the retention conditions. Finally, numerical results are shown to carefully reproduce experimental data on template devices with different gate stack compositions, validating the physical assumptions and making the model a valuable tool for nitride memories investigation and design. © 2010 Elsevier Ltd. All rights reserved. Source

Hermans J.V.,IMEC | Dai H.,Applied Materials | Niroomand A.,Micron | Laidler D.,IMEC | And 5 more authors.
Proceedings of SPIE - The International Society for Optical Engineering

For device manufacturing at the 10nm node (N10) and below, EUV lithography is one of the technology options to achieve the required resolution. Besides high throughput and extreme resolution, excellent wafer CD, overlay and defect control are also required. In this paper, we discuss two wafer CD uniformity issues, the effect of the reticle black border and photon shot noise. The readiness of EUV lithography for N10 will be discussed by showing on-product imaging and overlay performance of a self aligned via layer inserted with EUV lithography. EUV single patterning results will be discussed by comparing the imaging performance of our NXE:3100 cluster to the NXE:3300 at ASML. Last but not least, the extendibility of EUV lithography towards sub 10nm patterning will be discussed by demonstrating sub 10nm half pitch LS patterns with EUV single Self Aligned Double Patterning (SADP). © 2013 SPIE. Source

Fenger G.L.,Mentor Graphics | Lorusso G.F.,IMEC | Hendrickx E.,IMEC | Niroomand A.,Micron
Journal of Micro/Nanolithography, MEMS, and MOEMS

Extreme ultraviolet (EUV) lithography is currently the most promising technology for advanced manufacturing nodes. This study aims to assess in detail the quality of a full chip optical correction for a EUV design, as well to discuss the available approaches to compensate for EUV-specific effects. Extensive data sets have been collected on the ASML EUV Alpha-Demo Tool using the latest Interuniversity Microelectronics Center baseline resist Shin-Etsu SEVR59. In total ∼1300 critical dimension (CD) measurements at wafer level and 700 at mask level were used as input for model calibration and validation. The smallest feature size in the data set was 32 nm. Both one-dimensional and twodimensional structures through CD and pitch were measured. The reticle used in this calibration exercise allowed one to modulate flare by varying tiling densities. The shadowing effect was modeled by means of a single bias correction throughout the design. Horizontal and vertical features of different types through pitch and CD were used to calibrate the shadowing correction. The model calibration yielded an root-mean square of ∼1 nm, which was observed to improve by including reticle CD data. An EUV mask fully corrected for optical proximity correction, flare and shadowing was fabricated and qualified, demonstrating the effectiveness of the implemented corrections. © 2010 Society of Photo-Optical Instrumentation Engineers. Source

Boniardi M.,Polytechnic of Milan | Ielmini D.,Polytechnic of Milan | Lavizzari S.,Micron | Lacaita A.L.,Polytechnic of Milan | And 3 more authors.
IEEE Transactions on Electron Devices

The phase-change memory (PCM), based on the reversible phase transition in a chalcogenide material, is among the most attractive memory concepts for next-generation nonvolatile memories. Due to the metastable nature of the amorphous state, the memory can exhibit a time variation of resistance after programming as a result of two main mechanisms: 1) structural relaxation (SR), which is an atomic rearrangement to minimize the defect density, and 2) crystallization of the amorphous chalcogenide. SR has been mostly studied at the single-cell level, whereas a statistical analysis and modeling is necessary for device reliability estimation and prediction. This work studies the statistical behavior of SR in PCM devices, through experimental and modeling approaches. Statistical SR data from PCM arrays are shown, and a Monte Carlo model for SR statistics is proposed, based on previous physical modeling of the SR process. This model allows for long-term, physics-based, and array-level reliability extrapolations in large PCM arrays. © 2006 IEEE. Source

Pellizzer F.,Micron | Bez R.,Micron
ICICDT 2012 - IEEE International Conference on Integrated Circuit Design and Technology

In this paper we will review the evolution of Phase-Change Memories (PCM) through the last decade, starting from the first electrical results on single cells and ending with the latest news of multi-Gb chips. Entering into the sub-30nm realm, PCM is demonstrating the capability to enter the broad memory market and to become a mainstream technology. © 2012 IEEE. Source

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