Azadi E.,Urmia Microelectronics Research Laboratory |
Ghasemizadeh H.,Urmia Microelectronics Research Laboratory |
Khoei A.,Urmia Microelectronics Research Laboratory |
Hadidi K.,Urmia Microelectronics Research Laboratory
2010 5th International Symposium on Telecommunications, IST 2010 | Year: 2010
This paper presents 5Gb/s serial link transceiver. Input symbol rate is 6.25Gs/s. in each 10 symbols 2 symbol are used for line coding hence data rate is 5Gb/s. Transmitter uses 2-PAM signaling and pre-emphasis technique for compensation of channel low-pass characteristics and reduction of inter symbol interference (ISI). To achieve high data rate without speed critical logic on chip, the data are multiplexed when transmission, with 10:1 multiplexer. Hence input clock frequency reduced to 625 MHz. This parallelism is performed by using multiple phases that are tapped from a PLL and provides 10 clocks, each have 160ps delay rather than previous clock. With using line switching technique for multiplexing, the die- area was decreased. With different line coding, transmitter area and power consumption are decreased. Besides line equalization is relaxed. By using this line coding, a new architecture for clock data recovery (CDR) was presented that consumes low power and has good jitter characteristics. Besides receiver uses very accurate frequency acquisition architecture. Transceiver consumes 755mw power with 3.3v power supply and in worse condition, sampling clock in receiver, has 28.5ps jitter. The circuit was implemented in 0.35u CMOS process. © 2010 IEEE.