Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase II | Award Amount: 748.81K | Year: 2010
The development of advanced microelectronics for satellite communications applications have become increasingly expensive. Smaller feature-sized microelectronics fabrication is now needed to provide ICs for complex radiation-hardened communications systems operating in space. Historically, radiation-hardened integrated circuit (IC) components have been fabricated at dedicated foundries using specialty, hardened, larger-feature size, expensive processes while commercial foundries focus on producing high-performance, non-radiation tolerant, ICs using smaller and smaller feature size processes. Micro-RDC, a leading developer of technology for IC device hardening by design, instead of by process, has developed a family of 90nm Design-Hardened Structured Application Specific Integrated Circuits (DH SASICs) that can be produced on a commercial IC fabrication line using a Single Reticle, Multi-Project-Wafer. This enables satellite systems designers to develop high-performance radiation-hardened ICs, at a very low cost. This technology has gained much popularity lately amongst space communications IC designers, but the need for even higher speed devices now exists. This Phase II effort proposes to design, fabricate and test a proof-of-concept test chip to verify some of the key elements of a next generation 45nm SOI DH SASIC. This verification should demonstrate sufficient reduced program risk to entice an outside investor/developer to fund a Phase III development program. BENEFIT: Space Communications program designers are developing high-performance systems to provide advanced processing from space-based platforms. These systems require advanced, high-speed, radiation-hardened integrated circuits for data processing. High-Speed integrated circuits for specific processing functions that are radiation-hardened for space, currently either do not exist or are manufactured at great expense. These devices also tend to be large and require much power for operation. Commercial ICs are not tolerant to radiation effects and were not designed to meet military specifications. Micro-RDC’s previous 90nm Bulk CMOS Design-Hardened Structured ASIC program enables designers to develop advanced radiation-hardened digital ICs at a fraction of the cost and with much lower power demands. With even faster and more dense satellite system requirements now being developed Micro-RDC’s Design-Hardened Structured ASIC program needs to migrate to the next generation 45nm feature-size technology to meet the needs of even faster computing, with the benefit of SOI substrates for enhanced hardness.
Agency: National Aeronautics and Space Administration | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 125.00K | Year: 2014
Radiation Hardened Application Specific Integrated Circuits (ASICs) provide for the highest performance, lowest power and size for Space Missions. In order to dramatically reduce the development cycle and reduce the cost to tapeout Rad Hard ASICs, we propose a Structured ASIC approach. In this approach we fix an array of complex logic cells and provide a fixed Area Array for I/O pads supporting in excess of 400 CMOS GPIO pins. In addition, we fix the power grid and the pins associated with power (core and I/O) and ground. Thus, we require only routing in a subset of the metal layers in order to configure the Structured ASIC to a specific design. This leads to substantial reduction in design and verification time to tapeout, and results in reduced cost by requiring a subset of Mask changes per design. In this work, we will build on existing 90nm Silicon proven Radiation Hardened Structured ASIC platform and develop a Structured ASIC platform at the 45nm SOI technology node with the objective to increase the clock speeds to hundreds of MHz with SEU mitigation in sequential logic. We will also use High Density Interconnect (HDI) for packaging the Die in BGA and LGA packages. The HDI design does not change for each configuration of the Structured ASIC so that the same benefits of Structured ASIC are extended to packaging the part with high pinout and high speed I/O requirements eliminating layout design costs.
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase I | Award Amount: 150.00K | Year: 2014
ABSTRACT: Central Processing Units (CPUs) continue to grow in complexity while introducing higher speed clocks required to process data at extreme speeds. Advanced space grade, radiation-hardened processors are following this trend as processing requirements in space become more demanding, but for the full benefit to be derived from to faster CPUs support circuits must be developed that can match their speed requirements. A key component required to achieve high system throughput is a cache memory performance-matched to the CPU, including speed, radiation tolerance and power consumption. Discrete cache memories have been commercially available for many years built using various processes. Most products today are built in CMOS but do not deliver the speeds and radiation tolerance required of future space-grade systems. The goal of this project is to design and produce cache memory capable of supporting high performance space-grade CPUs with no wait-state memory accesses. Cache memory sizes must be sufficient to allow the CPU to operate at optimal speed while meeting all of the radiation, temperature and power supply parameters of the associated circuitry. Micro-RDC possesses design expertise, intellectual property and design tools capable of addressing these leading- edge goals with deliverables capable of supporting system requirements in the foreseeable future. BENEFIT: Delivery of cache memory performance-matched to high speed radiation hardened CPUs will support increased throughput of communications channels in satellite transponders as well as support other types of compute-intensive applications such as image processing and resource management. A high density 16 Mb monolithic SRAM L2 cache that can perform accesses at the MPU core frequency will significantly improve system processing performance.
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase II | Award Amount: 749.96K | Year: 2011
ABSTRACT: Micro-RDC will develop a low power, radiation hardened memory compilers suitable for use in current and future satellite missions. The memory compilers can quickly generate embedded memory blocks hardened against Total Ionizing Dose effects, Single Event Upsets, Single Event Latch-up, and Single Event Transients. The memory compiler supports a variety of different attributes including word length, aspect ratio, and memory types for several foundry processes and feature sizes to meet various application and radiation requirements. The BAE 150nm technology and the IBM 90nm Bulk plus IBM 45nm SOI processes will each have an SRAM compiler to provide a MegaRAD level Radiation Hardened-By-Design solution. These embedded SRAM blocks either have been, or will be fabricated and verified to meet the radiation hardened levels of this solicitation. The IBM 45nm 12SOI process is also supported to provide an advanced deep sub-micron SOI commercial foundry solution. The Micro-RDC compiler will supply all of the Computer Aided Design (CAD) files required to integrate with standard ASIC design flows. BENEFIT: High performance ASICs are expected to provide most of the processing functions in advanced satellite systems. These devices require large amounts of on-chip memory to prevent memory bandwidth limitations from stalling the processors. In the commercial realm, memory compilers are used to quickly and automatically design embedded memory blocks with a variety of different attributes including word size, aspect ratio, memory type, access time, and power dissipation. ASICs for space applications are not supported by standard commercial memory compilers. This is due to the complications associated with developing compilers to incorporate the unique aspects of space electronics such as radiation hardness, low power, and reliability. The Low Power, Radiation Hardened Memory Compiler developed under this effort provides a cost effective means for system designers to develop Radiation Hardened ASICs for space systems. Micro-RDC will enhance and maintain the Radiation Hardened Embedded Memory Compiler as fabrication technologies advance funding these activities out of commercial sales. This will provide an up-to-date compiler independent of fabrication facility that keeps to date with cost-effective volume of scale manufacturing for Radiation Hardened Embedded Memory.
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase II | Award Amount: 749.96K | Year: 2015
ABSTRACT: The E-Band frequency bands from 71 to 76 GHz and 81 to 86 GHz have been designated for satellite down- and uplinks, and have gained an increased interest. The wide bandwidth in excess of 1GHz allows the use of low order modulation schemes and simple receiver implementation. In other words, coarser Analog to Digital converters (ADC) and Digital to Analog (DAC) converters can be used in the RF front end. In this research, we will design the ADC and DAC using Second Order Delta Sigma Modulation techniques which achieve equivalent high oversampling by adding multiple paths and interleaved sampling while keeping the base sampling frequency low. The objective is to add paths to meet the requirement for 1GHz bandwidth and 9 bits effective number of bits. With Delta Sigma Modulation we can design monolithic System on a Chip solutions with integrated ADCs and DACs. The high density of the technology node can be exploited for implementing the System on a Chip capable of processing the high band width signals and providing the high speed host interface for space-borne communication systems. The Delta Sigma Modulators will be taped out in the Radiation Hardened 32nm SOI CMOS process. BENEFIT: Communication in the E-Band has established itself not only in point to point terrestrial links, but also satellite links to ground and inter satellite communications. The ADC and DACs developed in this project have a growing market in commercial E-Band communications. By designing the ADC and DAC using the Radiation Hardened 32nm SOI process, monolithic System on a Chip solutions with integrated ADC and DACs can be developed that save on cost, power and size while achieving the multi-GHz bandwidth requirements for E-Band communication in Space. Due to the high bandwidth required in E-Band, the ADC and DACs designed in this project can more than satisfy the demands for WiFi and 5G monolithic System on a Chip radio solutions where we can tradeoff bandwidth for even more power savings. Therefore, the demand for the chips extend beyond E-band and can benefit from higher volumes in these bands to expand the market and reduce costs.