Agency: National Aeronautics and Space Administration | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 125.00K | Year: 2014
Radiation Hardened Application Specific Integrated Circuits (ASICs) provide for the highest performance, lowest power and size for Space Missions. In order to dramatically reduce the development cycle and reduce the cost to tapeout Rad Hard ASICs, we propose a Structured ASIC approach. In this approach we fix an array of complex logic cells and provide a fixed Area Array for I/O pads supporting in excess of 400 CMOS GPIO pins. In addition, we fix the power grid and the pins associated with power (core and I/O) and ground. Thus, we require only routing in a subset of the metal layers in order to configure the Structured ASIC to a specific design. This leads to substantial reduction in design and verification time to tapeout, and results in reduced cost by requiring a subset of Mask changes per design. In this work, we will build on existing 90nm Silicon proven Radiation Hardened Structured ASIC platform and develop a Structured ASIC platform at the 45nm SOI technology node with the objective to increase the clock speeds to hundreds of MHz with SEU mitigation in sequential logic. We will also use High Density Interconnect (HDI) for packaging the Die in BGA and LGA packages. The HDI design does not change for each configuration of the Structured ASIC so that the same benefits of Structured ASIC are extended to packaging the part with high pinout and high speed I/O requirements eliminating layout design costs.
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase I | Award Amount: 150.00K | Year: 2014
ABSTRACT: Central Processing Units (CPUs) continue to grow in complexity while introducing higher speed clocks required to process data at extreme speeds. Advanced space grade, radiation-hardened processors are following this trend as processing requirements in space become more demanding, but for the full benefit to be derived from to faster CPUs support circuits must be developed that can match their speed requirements. A key component required to achieve high system throughput is a cache memory performance-matched to the CPU, including speed, radiation tolerance and power consumption. Discrete cache memories have been commercially available for many years built using various processes. Most products today are built in CMOS but do not deliver the speeds and radiation tolerance required of future space-grade systems. The goal of this project is to design and produce cache memory capable of supporting high performance space-grade CPUs with no wait-state memory accesses. Cache memory sizes must be sufficient to allow the CPU to operate at optimal speed while meeting all of the radiation, temperature and power supply parameters of the associated circuitry. Micro-RDC possesses design expertise, intellectual property and design tools capable of addressing these leading- edge goals with deliverables capable of supporting system requirements in the foreseeable future. BENEFIT: Delivery of cache memory performance-matched to high speed radiation hardened CPUs will support increased throughput of communications channels in satellite transponders as well as support other types of compute-intensive applications such as image processing and resource management. A high density 16 Mb monolithic SRAM L2 cache that can perform accesses at the MPU core frequency will significantly improve system processing performance.
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase II | Award Amount: 749.96K | Year: 2011
ABSTRACT: Micro-RDC will develop a low power, radiation hardened memory compilers suitable for use in current and future satellite missions. The memory compilers can quickly generate embedded memory blocks hardened against Total Ionizing Dose effects, Single Event Upsets, Single Event Latch-up, and Single Event Transients. The memory compiler supports a variety of different attributes including word length, aspect ratio, and memory types for several foundry processes and feature sizes to meet various application and radiation requirements. The BAE 150nm technology and the IBM 90nm Bulk plus IBM 45nm SOI processes will each have an SRAM compiler to provide a MegaRAD level Radiation Hardened-By-Design solution. These embedded SRAM blocks either have been, or will be fabricated and verified to meet the radiation hardened levels of this solicitation. The IBM 45nm 12SOI process is also supported to provide an advanced deep sub-micron SOI commercial foundry solution. The Micro-RDC compiler will supply all of the Computer Aided Design (CAD) files required to integrate with standard ASIC design flows. BENEFIT: High performance ASICs are expected to provide most of the processing functions in advanced satellite systems. These devices require large amounts of on-chip memory to prevent memory bandwidth limitations from stalling the processors. In the commercial realm, memory compilers are used to quickly and automatically design embedded memory blocks with a variety of different attributes including word size, aspect ratio, memory type, access time, and power dissipation. ASICs for space applications are not supported by standard commercial memory compilers. This is due to the complications associated with developing compilers to incorporate the unique aspects of space electronics such as radiation hardness, low power, and reliability. The Low Power, Radiation Hardened Memory Compiler developed under this effort provides a cost effective means for system designers to develop Radiation Hardened ASICs for space systems. Micro-RDC will enhance and maintain the Radiation Hardened Embedded Memory Compiler as fabrication technologies advance funding these activities out of commercial sales. This will provide an up-to-date compiler independent of fabrication facility that keeps to date with cost-effective volume of scale manufacturing for Radiation Hardened Embedded Memory.
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase I | Award Amount: 99.74K | Year: 2011
ABSTRACT: We propose a new radiation-hardened star tracker system which will provide high-precision performance while meeting all radiation requirements listed in the solicitation. It has a baffle, focal-plane arrays, microprocessor, memory and power supply. The key component is a high-performance microprocessor fabricated using the Micro-RDC rad-hard Structured ASIC process. This is a low cost solution to implement the rad-hard microprocessor and communication interfaces including Space Wire, I2C, and USB. In addition, the system will include a rad-hard memory and CMOS active pixel sensor (APS). The system has a simple architecture with a small number of components. The star tracker will have total ionizing dose (TID) tolerance greater than 1 Mrad (Si). The performance degradation of the star tracker at 300 krad(Si) will be less than 30%. The star tracker will have an inertial pointing measurement error of less than 1 arc-second. The star tracker can continue to operate at track rate slew up to 2 degrees per second. The"lost in space"feature will be included, too. BENEFIT: The target market of the radiation hardened star tracker includes all satellite or space applications that need attitude information, especially these satellites required to work for long time in radiation environment or following a high dose rate event. For general commercial satellite, the radiation hardened star tracker can extend the life time of whole system and work more robustly in some harsh space environments, such as"space storm"when Sun activity peaks. The proposed star tracker has the advantage of high radiation tolerance, high accuracy and low power. Comparing to existing start trackers, our star tracker is competent for high reliability and long term space applications, especially for military satellites. In addition, the radiation hardened computing part can be used in all space applications that needs low power, high performance and radiation tolerance. The application is much wider than the star tracker.
Agency: National Aeronautics and Space Administration | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 99.96K | Year: 2011
The objective of the Phase-I research is to design a multi-GHz high bandwidth Delta Sigma Analog-to-Digital and Digital-to-Analog converter using a deep sub-micron CMOS process. Since the Delta Sigma Modulation ADC samples in the multi-GHz range, direct sampling and conversion to digital of post LNA Microwave signals is possible. By targeting the ADC on a CMOS technology node (90nm, 65nm or 45nm), a complete all digital radio receiver and demodulator can be implemented on the same System on a Chip that performs host interface and higher network level protocols. Using Delta Sigma Modulation at GHz sampling rates eliminates the anti-aliasing filter requirement. The all digital receiver eliminates I/Q imbalance due to the receiver and DC offset introduced by zero-IF architectures. In order to support multi GHz sampling rates in CMOS, advanced time interleaving, parallel Delta Sigma Modulators and shared integrator architectures are considered. Using Micro-RDC RHBD cells and design experience the digital filtering and decimation of the high frequency bit stream are hardened. The baseband filtering is implemented with temporal latch technology for SEU immunity. In this research various hardening techniques will be used to harden the analog sub-components in the Delta Sigma Modulator including investigating pipelining and parallel processing architectures for filtering and decimation which also address low power requirements.