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Hou D.,Nanjing Southeast University | Hou D.,Institute of Microelectronics, Singapore | Hong W.,Nanjing Southeast University | Goh W.-L.,Nanyang Technological University | And 4 more authors.
IEEE Antennas and Propagation Magazine | Year: 2014

In this paper, on-chip higher-order-mode dielectric-resonator antennas (DRAs), fed by a half-mode-backed cavity structure using standard CMOS technology, are presented. With the dominant cavity mode (half-TEz100), the half-mode cavity-feeding structure provided a high antenna radiation efficiency. The dielectric resonators (DRs) were designed to operate at higher-order modes (TEx¿13, TEx¿15) to enhance the antenna gain. At around 135 GHz, the proposed antennas demonstrated measured gains of 6.2 dBi and 7.5 dBi for the TEx¿13 and TEx¿15 modes, respectively, with corresponding simulated radiation efficiencies of 46% and 42%. Both antennas had a measured impedance bandwidth of 7%. The proposed antennas not only accomplished high gain without occupying a large chip area, but also maintained comparable or even improved cost performance and simplicity over other on-chip antennas. © 1990-2011 IEEE.

Hou D.,Nanjing Southeast University | Hou D.,Agency for Science, Technology and Research Singapore | Xiong Y.-Z.,Agency for Science, Technology and Research Singapore | Xiong Y.-Z.,MicroArray Technologies Co. | And 4 more authors.
IEEE Transactions on Antennas and Propagation | Year: 2012

This work discusses the design methodologies of 130-GHz high gain and high efficiency on-chip meander slot antennas in a standard CMOS technology. In the proposed structure, stacked dielectric resonators (DRs) are placed on the top of the on-chip feeding element to form series-fed antenna array for antenna gain and efficiency improvement. The integrated antenna with double stacked DRs achieved a measured gain of 4.7 dBi at 130 GHz with a bandwidth of 11%. The antenna size is 0.8 × 0.9mm 2 and the simulation results indicate a radiation efficiency of 43%. To the best of our knowledge, this is the first demonstration of an on-chip antenna gain and efficiency enhancement through stacked DRs. © 2012 IEEE.

Hou D.,Nanjing Southeast University | Hou D.,Institute of Microelectronics, Singapore | Xiong Y.-Z.,MicroArray Technologies Co. | Goh W.-L.,Nanyang Technological University | And 2 more authors.
IEEE Microwave and Wireless Components Letters | Year: 2012

This letter describes a D-band 3-stage cascode amplifier developed using the IHP 0.13 μ m SiGe BiCMOS technology. The amplifier is implemented with low-loss transformer for inter-stage matching and single-to-differential transformation. The large-signal characteristics of the cascode HBT configuration are used to optimize the bias condition for highest output power and gain performance. A measured amplifier achieves a peak power gain of 24.3 dB, with a 3 dB bandwidth of 20 GHz centered at 130 GHz. The amplifier exhibits a saturated output power of 7.7 dBm and an output 1 dB gain compression point of 6 dBm with a power consumption of 84 mW. The measured noise figure is 6.8 dB at 130 GHz and stays under 8 dB over the 3 dB bandwidth. To the best of our knowledge, the proposed amplifier exhibits the highest gain and output power among the silicon-based D-band amplifiers reported so far. © 2012 IEEE.

He J.,Institute of Microelectronics, Singapore | Xiong Y.-Z.,MicroArray Technologies Co. | Zhang Y.P.,Nanyang Technological University
IEEE Transactions on Microwave Theory and Techniques | Year: 2012

This paper proposes a new 60-GHz single-pole-double-throw (SPDT) switch. It is designed in a 1.2-V 130-nm bulk CMOS and has a small core area of 222 μm×92 μm. The switch exhibits measured insertion loss of 1.7 dB, isolation of 22 dB, input return loss of 20 dB, output return loss of 14 dB, and simulated power-handling capability of 13.8 dBm at 60 GHz. The proposed SPDT switch demonstrates such superior performances and consumes a much smaller die area to those of other SPDT switches, and therefore has potential to be used in highly integrated 60-GHz CMOS radios. © 1963-2012 IEEE.

Hou D.,Nanjing Southeast University | Hou D.,Institute of Microelectronics, Singapore | Hou D.,Nanyang Technological University | Hong W.,Nanjing Southeast University | And 5 more authors.
IEEE MTT-S International Microwave Symposium Digest | Year: 2012

This paper describes a D-band on-chip rat-race coupler using a novel phase inverter and developed in a standard CMOS process. The simple structural phase inverter which is based on the characteristic impedance and phase difference analysis has demonstrated its potential for wideband and compact millimeter-wave frequency range applications. The developed rat-race coupler using the proposed phase inverter, features a 40% size reduction and over 60% bandwidth improvement compared to conventional structures. In the complete D-band range, measured amplitude and phase imbalances for the coupler are within 0.5 dB and 15°, respectively. The port-to-port isolation is better than 25 dB in the D-band range with the highest value of 41 dB at 118 GHz. The insertion loss achieves L.2 ± 0.3 dB and the coral size of the coupler is only 290 × 162 μm 2. The proposed coupler has a huge potential for integration in single-chip systems over 100 GHz. © 2012 IEEE.

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