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Albuquerque, United States

Meyer-Base U.,Florida A&M University | Vera A.,Micro RDC | Vera A.,University of New Mexico | Meyer-Base A.,Florida A&M University | And 2 more authors.
IEEE Transactions on Education | Year: 2010

In this paper, an innovative educational approach to introducing undergraduates to both digital signal processing (DSP) and field programmable gate array (FPGA)-based design in a one-semester course and laboratory is described. While both DSP and FPGA-based courses are currently present in different curricula, this integrated approach reduces the number of electives students would have to take and at the same time provides a hands-on DSP experience. Developing such a new course with no textbook available is challenging. Therefore, the educational materials developed, the software tool evaluations, and topics to be covered in lectures and laboratories are described. Detailed evaluations of the selection of appropriate software and hardware platforms, topics to cover, and student feedback are provided. © 2006 IEEE. Source

Vera G.A.,Micro RDC | Ardalan. S.,Micro RDC | Avery K.,Air Force Research Lab
AIAA Infotech at Aerospace 2010 | Year: 2010

Memory scrubbing is used to mitigate SEU on susceptible devices. In the case of FPGAs, configuration memory scrubbing is generally used in conjunction with triple modular redundancy (TMR) to increase the reliability of FPGA systems in space borne applications. Reported solutions require a subsystem able to read and write from the configuration memory and retrieve from a "safe storage" a golden bitstream for scrubbing whenever an error is detected. An alternative to this solution is to implement error detection and correction codes. These codes usually require data to be embedded within the data that is being protected, which is particularly difficult in the case of a configuration bitstream since it is automatically created by CAD tools. In this paper we present an alternative error correction and detection implementation that overcomes such difficulties and allows fast local scrubbing without the need of storing a golden bitstream somewhere safe. This implementation is a processing peripheral tied to a scrubber -labeled Femto- currently being implemented in a RHBD S-ASIC. Copyright © 2010 by the American Institute of Aeronautics and Astronautics, Inc. Source

Buchner S.,Global Strategies Group | Sibley M.,Micro RDC | Eaton P.,Micro RDC | Mavis D.,Micro RDC | McMorrow D.,U.S. Navy
IEEE Transactions on Nuclear Science | Year: 2010

Pulsed laser light has been used to reveal how total ionizing dose radiation affects the propagation of single event transients in a string of inverters. By holding the input to the string of inverters at high voltage (1.8 V) during exposure to ionizing radiation, an asymmetry in the threshold voltages of the n-channel transistors is induced, i.e., the inputs to the inverters alternate between high and low voltage, which results in every odd-numbered n-channel transistor experiencing more Total Ionizing Dose (TID) degradation than the even-numbered n-channel transistors. The asymmetry manifests itself as an additional broadening of laser-light induced transients when the input to the string of inverters is set to low voltage and a contraction of the transients when the input is set to high voltage. Exposure of the inverter string to heavy ions with a fixed input voltage resulted in a contraction of the transients, regardless of whether the input was at high or low voltage, behavior that is consistent with the results from pulsed laser testing. © 2010 IEEE. Source

Vera G.A.,Micro RDC | Sibley M.,Micro RDC | Ardalan S.,Micro RDC | Avery K.,Air Force Research Lab | Lyke J.,Air Force Research Lab
AIAA Infotech at Aerospace 2010 | Year: 2010

Appliqué Sensor Interface Modules (ASIMs) provide a convenient implementation of the Space Plug-and-Play Avionics (SPA) standard for common spacecraft devices. ASIMs simplify the chore of interfacing to SPA by providing automatic support for the low-level physical interface, electronic datasheets, synchronization, and power management. ASIMs have been implemented in an array of technologies, including programmable logic devices. In this paper we describe the first ASIM design based in a radiation hardened by design (RHBD) structured application specific integrated circuit (S-ASIC) fabric, based on the IBM 90nm bulk CMOS process, leveraging one of the processes used in the trusted foundry. This implementation, capable of supporting either SPA-U (USB) or SPA-S (Spacewire), is expected to result in the most-compact and power-efficient rad-hard ASIM design yet implemented. Source

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