Fremont, CA, United States
Fremont, CA, United States

Mentor Graphics, Inc is a US-based multinational corporation dealing in electronic design automation for electrical engineering and electronics. In 2004 it was ranked third in the EDA industry it helped create. Founded in 1981, the company is headquartered in Wilsonville, Oregon and employs roughly 4,400 people worldwide with annual revenues of around $1 billion. Wikipedia.


Time filter

Source Type

Patent
Mentor Graphics | Date: 2016-06-21

Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.


Patent
Mentor Graphics | Date: 2016-07-26

The invention concerns a method of designing a prototype comprising a plurality of programmable chips, such as FPGA chips, for modelling an ASIC circuit, said ASIC circuit being intended to implement a logic design comprising a hierarchy of logic modules communicating together. The method according to the invention comprises the steps of:partitioning the hierarchy of logic modules into regions each comprising one or a plurality of programmable chips, while minimising:inter-region communications in a manner correlated to the physical connections available between each pair of programmable chips;and the number of crossings of programmable chips of a critical combinatorial path;establishing a routing of the signals between programmable chips using the physical resources available.


Patent
Mentor Graphics | Date: 2016-07-11

Aspects of the disclosed technology relate to techniques of design implementation for FPGA prototyping. An initial FPGA-mapped netlist and a generic RTL design associated with the initial FPGA-mapped netlist are generated based on an original RTL (register-transfer level) design for a circuit design and optionally on verification-related features. Based on the initial FPGA-mapped netlist, the circuit design is partitioned into design partitions for implementing the circuit design across a plurality of FPGA chips. Final FPGA-mapped netlists are then generated based on the design partitions represented by the generic RTL design or by a combination of the generic RTL design and the initial FPGA-mapped netlist.


Patent
Mentor Graphics | Date: 2016-09-12

Aspects of the invention relate to yield analysis techniques for generating root cause candidates for yield analysis. With various implementations of the invention, points of interest are first identified in a layout design. Next, regions of interest are determined for the identified points of interest. Next, one or more properties are extracted from the regions of interest. Based at least on the one or more properties, diagnosis reports of failing devices fabricated according to the layout design are analyzed to identify probable root causes.


Patent
Mentor Graphics | Date: 2014-08-29

This application discloses a system to detect meta-stable glitches in a signal, such as an output of latch or other storage element. The system can include a sampling circuit configured to sample an output of a storage element. The system can include a mono-shot circuit configured to monitor the output of the storage element and generate a pulse when the monitored output of the storage element differs from the sampled output. The system can include a drive circuit configured to generate a glitch signal based, at least in part, on the sampled output, and to output the glitch signal in response to the pulse from the mono-shot circuit. The system can include an error detection circuit configured to receive the sampled output from the sampling circuit and the glitch signal from the drive circuit, and to generate an error signal when the sampled output differs from the glitch signal.


Patent
Mentor Graphics | Date: 2016-11-22

Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as fill regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or windows, and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient. Additionally, some implementations may allow a user to simultaneously optimize the density of multiple layers of a circuit by adding fill polygons to multiple layers of a circuit design simultaneously. Representations of sections of a multilayer fill structure will then be added to corresponding layers the circuit design until a specified target density is met.


Grant
Agency: European Commission | Branch: H2020 | Program: ECSEL-RIA | Phase: ECSEL-07-2015 | Award Amount: 9.71M | Year: 2016

The European lighting industry aims at reducing cost, at continuously improving product performance while reducing time to market and enlarging the product. The main challenge for the design in of LED components into lighting systems is the temperature and current dependence of their performance. In order to achieve a good design of LED systems, a modular, multi-physics based modelling approach is needed this way allowing the freedom for LED component integrators to use such models in any kind of luminaire designs. In order to overcome those key challenges, seamless integration of the LED in the product development chain is necessary. For that a bridge, in the form of standardization, has to be established between the semiconductor industry and the LED component integrators. In order to achieve this, the following tools have to be provided: Generic, multi-domain model of LED chips Compact thermal model of the LED chips environment Modeling interface towards the luminaire The goal of the project is to develop a standardized method to create multi-domain LED compact models from testing data. The objectives are: Define set of LED model equations that can be implemented into a FEM/CFD tool, for the purpose of self-consistent multi-domain simulation of LEDs thermal, electrical and light output characteristics. Provide interfacing between measurement tools, modelling tools and simulation tools to allow the application of the compact LED models. Prove the benefits of the use of compact models in the development process to reduce development times and cost. This will lead to an industry standard in the lighting industry. Achievement of this project is expected to boost time to market of LED products cut by 1/3, cut development cost by 50%, reduce Cost of Non-quality by 25%. The European lighting industry is offered a unique competitive advantage, necessary to catch the 30-40% speed of growth of its LED market and tape into potential new markets.


Patent
Mentor Graphics | Date: 2016-01-29

This application discloses a computing system implementing a source application to extract coverage data from a source database with application program interface (API) routines specific to the source database, and classify the coverage data according to a Unified Coverage Interoperability Standard (UCIS)-compliant format. The coverage data can include at least one of data from verification operations performed on a circuit design, test information utilized during the verification operations, or at least one test plan. The computing system implementing the source application can, based on the classification, select exchange routines to transfer the coverage data towards a target database. The computing system can implement a target application to utilize the classification of the coverage data to identify corresponding API routines specific to the target database, and write the coverage data to the target database with the identified API routines.


This application discloses a computing system configured to identify a channel in an electronic device is configured to transmit signals encoding data with more than two value levels in response to a correlated test input. The computing system can determine probabilities of value level changes in the transmitted signals based on an encoding for the correlated test input, and measure a step response of the channel. The computing system can perform statistical simulation or analysis on the channel based, at least in part, on the step response of the channel and the determined probabilities of value level changes in the transmitted signals, which can predict a signal integrity of the channel configured to transmit the signals based, at least in part, on the determined probabilities of value level changes in the transmitted signals.


Patent
Mentor Graphics | Date: 2016-07-07

This application discloses a computing system implementing a synthesis tool to synthesize a circuit design of an electronic system into a gate-level netlist having a logical hierarchy, utilize the gate-level netlist to generate a physical representation of the circuit design, and partition the circuit design into sub-designs based on the physical representation of the circuit design. The computing system can generate physical modules having self-contained physical definitions from the sub-designs, and reassemble the physical modules into a gate-level netlist having a physical hierarchy corresponding to the partitions of the circuit design. The computing system also can regroup modules in the circuit design based on the physical hierarchy, modify the circuit design to have the physical hierarchy based on the regrouped modules, and synthesize the modified circuit design into the gate-level netlist having the physical hierarchy.

Loading Mentor Graphics collaborators
Loading Mentor Graphics collaborators