Fremont, CA, United States
Fremont, CA, United States

Mentor Graphics, Inc is a US-based multinational corporation dealing in electronic design automation for electrical engineering and electronics. In 2004 it was ranked third in the EDA industry it helped create. Founded in 1981, the company is headquartered in Wilsonville, Oregon and employs roughly 4,400 people worldwide with annual revenues of around $1 billion. Wikipedia.


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Patent
Mentor Graphics | Date: 2016-06-21

Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.


Patent
Mentor Graphics | Date: 2016-07-26

The invention concerns a method of designing a prototype comprising a plurality of programmable chips, such as FPGA chips, for modelling an ASIC circuit, said ASIC circuit being intended to implement a logic design comprising a hierarchy of logic modules communicating together. The method according to the invention comprises the steps of:partitioning the hierarchy of logic modules into regions each comprising one or a plurality of programmable chips, while minimising:inter-region communications in a manner correlated to the physical connections available between each pair of programmable chips;and the number of crossings of programmable chips of a critical combinatorial path;establishing a routing of the signals between programmable chips using the physical resources available.


Patent
Mentor Graphics | Date: 2016-07-11

Aspects of the disclosed technology relate to techniques of design implementation for FPGA prototyping. An initial FPGA-mapped netlist and a generic RTL design associated with the initial FPGA-mapped netlist are generated based on an original RTL (register-transfer level) design for a circuit design and optionally on verification-related features. Based on the initial FPGA-mapped netlist, the circuit design is partitioned into design partitions for implementing the circuit design across a plurality of FPGA chips. Final FPGA-mapped netlists are then generated based on the design partitions represented by the generic RTL design or by a combination of the generic RTL design and the initial FPGA-mapped netlist.


Patent
Mentor Graphics | Date: 2016-09-12

Aspects of the invention relate to yield analysis techniques for generating root cause candidates for yield analysis. With various implementations of the invention, points of interest are first identified in a layout design. Next, regions of interest are determined for the identified points of interest. Next, one or more properties are extracted from the regions of interest. Based at least on the one or more properties, diagnosis reports of failing devices fabricated according to the layout design are analyzed to identify probable root causes.


Patent
Mentor Graphics | Date: 2016-11-22

Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as fill regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or windows, and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient. Additionally, some implementations may allow a user to simultaneously optimize the density of multiple layers of a circuit by adding fill polygons to multiple layers of a circuit design simultaneously. Representations of sections of a multilayer fill structure will then be added to corresponding layers the circuit design until a specified target density is met.


Patent
Mentor Graphics | Date: 2016-10-03

Disclosed herein are representative embodiments of methods, systems, and apparatus that can used to control real-time events (e.g., the real-time clock) during the design, simulation, or verification of an embedded system. In one exemplary embodiment disclosed herein, for example, a real-time clock signal is generated and tasks defined by an embedded software application are triggered with the real-time clock signal. In this embodiment, the embedded software application is executed by an embedded processor with a real-time operating system (RTOS), and the real-time clock signal is controllable independent of a processor clock signal driving the embedded processor in a manner that allows the real-time clock to have a different time base than the processor clock.


Patent
Mentor Graphics | Date: 2016-01-20

This application discloses a computing system to simulate a wafer image based on a mandrel mask and a block mask to be utilized to print a final wafer image on a substrate. To simulate the wafer image the computing system can estimate dummy sidewalls based on the mandrel mask, estimate contours of the block mask, and determine the simulated wafer image based on differences between the dummy sidewalls and the estimated contours of the block mask. The computing system can compare the simulated wafer image against a target wafer image in a layout design to identify hotspots where the simulated wafer image deviates from the target wafer image. Based on the identified hotspots, the computing system can modify the target wafer image in the layout design, prioritize edge modification in a subsequent optical proximity correction process, or modify computation of image error, which drives the optical proximity correction process.


Patent
Mentor Graphics | Date: 2016-01-27

This application discloses a controller area network node including a controller and a transceiver. The transceiver includes security circuitry to perform various security checks on messages the controller area network node intends to have transmitted over a shared bus in a controller area network. The security circuitry can determine whether the messages conform to the rules associated with a design and a traffic scheduling of the controller area network. Some of those rules include that the controller area network node transmit messages with identifiers that were assigned to the controller area network node, or transmit messages with a specified timing. When the security circuitry identifies one of the messages fails to conform to the rules for the controller area network, the security circuitry can initiate a security action, such as refusing or delaying transmission of the messages or reporting the rules violation to the controller.


Aspects of the disclosed technology relate to techniques of combining directed self-assembly lithography and multiple patterning lithography. A coloring/grouping graph is first generated from layout data of a layout design. In the coloring/grouping graph, each coloring edge connects two nodes representing layout features that must be assigned to different masks, and each grouping/coloring edge connects two nodes representing layout features that should either be grouped together for DSA (directed-self-assembly) lithography or be assigned to different masks for multiple patterning lithography. The node groups formed by nodes connected with the coloring edges are colored. Colors of the nodes in one or more of node groups connected by the grouping/coloring edges are adjusted to convert one or more of the grouping/coloring edges into the coloring edges. After conversion, layout features represented by the nodes directly connected with the grouping/coloring edges are grouped together for generating guiding patterns.


Grant
Agency: European Commission | Branch: H2020 | Program: ECSEL-RIA | Phase: ECSEL-07-2015 | Award Amount: 9.71M | Year: 2016

The European lighting industry aims at reducing cost, at continuously improving product performance while reducing time to market and enlarging the product. The main challenge for the design in of LED components into lighting systems is the temperature and current dependence of their performance. In order to achieve a good design of LED systems, a modular, multi-physics based modelling approach is needed this way allowing the freedom for LED component integrators to use such models in any kind of luminaire designs. In order to overcome those key challenges, seamless integration of the LED in the product development chain is necessary. For that a bridge, in the form of standardization, has to be established between the semiconductor industry and the LED component integrators. In order to achieve this, the following tools have to be provided: Generic, multi-domain model of LED chips Compact thermal model of the LED chips environment Modeling interface towards the luminaire The goal of the project is to develop a standardized method to create multi-domain LED compact models from testing data. The objectives are: Define set of LED model equations that can be implemented into a FEM/CFD tool, for the purpose of self-consistent multi-domain simulation of LEDs thermal, electrical and light output characteristics. Provide interfacing between measurement tools, modelling tools and simulation tools to allow the application of the compact LED models. Prove the benefits of the use of compact models in the development process to reduce development times and cost. This will lead to an industry standard in the lighting industry. Achievement of this project is expected to boost time to market of LED products cut by 1/3, cut development cost by 50%, reduce Cost of Non-quality by 25%. The European lighting industry is offered a unique competitive advantage, necessary to catch the 30-40% speed of growth of its LED market and tape into potential new markets.

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